Lines Matching +full:break +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Tests for Hyper-V features enablement
18 * but to activate the feature it is sufficient to set it to a non-zero
32 uint64_t control; member
47 GUEST_ASSERT(msr->idx); in guest_msr()
49 if (msr->write) in guest_msr()
50 vector = wrmsr_safe(msr->idx, msr->write_val); in guest_msr()
52 if (!vector && (!msr->write || !is_write_only_msr(msr->idx))) in guest_msr()
53 vector = rdmsr_safe(msr->idx, &msr_val); in guest_msr()
55 if (msr->fault_expected) in guest_msr()
58 msr->write ? "WR" : "RD", msr->idx, vector); in guest_msr()
62 msr->write ? "WR" : "RD", msr->idx, vector); in guest_msr()
64 if (vector || is_write_only_msr(msr->idx)) in guest_msr()
67 if (msr->write) in guest_msr()
70 msr->idx, msr->write_val, msr_val); in guest_msr()
72 /* Invariant TSC bit appears when TSC invariant control MSR is written to */ in guest_msr()
73 if (msr->idx == HV_X64_MSR_TSC_INVARIANT_CONTROL) { in guest_msr()
90 GUEST_ASSERT_NE(hcall->control, 0); in guest_hcall()
95 if (!(hcall->control & HV_HYPERCALL_FAST_BIT)) { in guest_hcall()
102 vector = __hyperv_hypercall(hcall->control, input, output, &res); in guest_hcall()
103 if (hcall->ud_expected) { in guest_hcall()
105 "Expected #UD for control '%lu', got vector '0x%x'", in guest_hcall()
106 hcall->control, vector); in guest_hcall()
109 "Expected no exception for control '%lu', got vector '0x%x'", in guest_hcall()
110 hcall->control, vector); in guest_hcall()
111 GUEST_ASSERT_EQ(res, hcall->expect); in guest_hcall()
120 * Enable all supported Hyper-V features, then clear the leafs holding in vcpu_reset_hv_cpuid()
154 prev_cpuid = allocate_kvm_cpuid2(vcpu->cpuid->nent); in guest_test_msrs_access()
166 * Only available when Hyper-V identification is set in guest_test_msrs_access()
168 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
169 msr->write = false; in guest_test_msrs_access()
170 msr->fault_expected = true; in guest_test_msrs_access()
171 break; in guest_test_msrs_access()
173 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
174 msr->write = false; in guest_test_msrs_access()
175 msr->fault_expected = true; in guest_test_msrs_access()
176 break; in guest_test_msrs_access()
183 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
184 msr->write = true; in guest_test_msrs_access()
185 msr->write_val = HYPERV_LINUX_OS_ID; in guest_test_msrs_access()
186 msr->fault_expected = false; in guest_test_msrs_access()
187 break; in guest_test_msrs_access()
189 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
190 msr->write = false; in guest_test_msrs_access()
191 msr->fault_expected = false; in guest_test_msrs_access()
192 break; in guest_test_msrs_access()
194 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
195 msr->write = false; in guest_test_msrs_access()
196 msr->fault_expected = false; in guest_test_msrs_access()
197 break; in guest_test_msrs_access()
200 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
201 msr->write = false; in guest_test_msrs_access()
202 msr->fault_expected = true; in guest_test_msrs_access()
203 break; in guest_test_msrs_access()
206 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
207 msr->write = false; in guest_test_msrs_access()
208 msr->fault_expected = false; in guest_test_msrs_access()
209 break; in guest_test_msrs_access()
212 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
213 msr->write = true; in guest_test_msrs_access()
214 msr->write_val = 1; in guest_test_msrs_access()
215 msr->fault_expected = true; in guest_test_msrs_access()
216 break; in guest_test_msrs_access()
219 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
220 msr->write = false; in guest_test_msrs_access()
221 msr->fault_expected = true; in guest_test_msrs_access()
222 break; in guest_test_msrs_access()
225 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
226 msr->write = false; in guest_test_msrs_access()
227 msr->fault_expected = false; in guest_test_msrs_access()
228 break; in guest_test_msrs_access()
231 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
232 msr->write = true; in guest_test_msrs_access()
233 msr->write_val = 1; in guest_test_msrs_access()
234 msr->fault_expected = true; in guest_test_msrs_access()
235 break; in guest_test_msrs_access()
238 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
239 msr->write = false; in guest_test_msrs_access()
240 msr->fault_expected = true; in guest_test_msrs_access()
241 break; in guest_test_msrs_access()
244 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
245 msr->write = false; in guest_test_msrs_access()
246 msr->fault_expected = false; in guest_test_msrs_access()
247 break; in guest_test_msrs_access()
250 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
251 msr->write = true; in guest_test_msrs_access()
252 msr->write_val = 1; in guest_test_msrs_access()
253 msr->fault_expected = true; in guest_test_msrs_access()
254 break; in guest_test_msrs_access()
257 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
258 msr->write = false; in guest_test_msrs_access()
259 msr->fault_expected = true; in guest_test_msrs_access()
260 break; in guest_test_msrs_access()
263 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
264 msr->write = false; in guest_test_msrs_access()
265 msr->fault_expected = false; in guest_test_msrs_access()
266 break; in guest_test_msrs_access()
268 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
269 msr->write = true; in guest_test_msrs_access()
276 msr->write_val = 0; in guest_test_msrs_access()
277 msr->fault_expected = false; in guest_test_msrs_access()
278 break; in guest_test_msrs_access()
281 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
282 msr->write = false; in guest_test_msrs_access()
283 msr->fault_expected = true; in guest_test_msrs_access()
284 break; in guest_test_msrs_access()
287 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
288 msr->write = false; in guest_test_msrs_access()
289 msr->fault_expected = false; in guest_test_msrs_access()
290 break; in guest_test_msrs_access()
292 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
293 msr->write = true; in guest_test_msrs_access()
294 msr->write_val = 0; in guest_test_msrs_access()
295 msr->fault_expected = false; in guest_test_msrs_access()
296 break; in guest_test_msrs_access()
299 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
300 msr->write = false; in guest_test_msrs_access()
301 msr->fault_expected = true; in guest_test_msrs_access()
302 break; in guest_test_msrs_access()
308 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
309 msr->write = false; in guest_test_msrs_access()
310 msr->fault_expected = true; in guest_test_msrs_access()
311 break; in guest_test_msrs_access()
314 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
315 msr->write = false; in guest_test_msrs_access()
316 msr->fault_expected = false; in guest_test_msrs_access()
317 break; in guest_test_msrs_access()
319 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
320 msr->write = true; in guest_test_msrs_access()
321 msr->write_val = 0; in guest_test_msrs_access()
322 msr->fault_expected = false; in guest_test_msrs_access()
323 break; in guest_test_msrs_access()
326 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
327 msr->write = false; in guest_test_msrs_access()
328 msr->fault_expected = true; in guest_test_msrs_access()
329 break; in guest_test_msrs_access()
332 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
333 msr->write = false; in guest_test_msrs_access()
334 msr->fault_expected = false; in guest_test_msrs_access()
335 break; in guest_test_msrs_access()
337 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
338 msr->write = true; in guest_test_msrs_access()
339 msr->write_val = 0; in guest_test_msrs_access()
340 msr->fault_expected = false; in guest_test_msrs_access()
341 break; in guest_test_msrs_access()
344 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
345 msr->write = true; in guest_test_msrs_access()
346 msr->write_val = 1 << 12; in guest_test_msrs_access()
347 msr->fault_expected = true; in guest_test_msrs_access()
348 break; in guest_test_msrs_access()
351 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
352 msr->write = true; in guest_test_msrs_access()
353 msr->write_val = 1 << 12; in guest_test_msrs_access()
354 msr->fault_expected = false; in guest_test_msrs_access()
355 break; in guest_test_msrs_access()
358 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
359 msr->write = false; in guest_test_msrs_access()
360 msr->fault_expected = true; in guest_test_msrs_access()
361 break; in guest_test_msrs_access()
364 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
365 msr->write = true; in guest_test_msrs_access()
366 msr->write_val = 1; in guest_test_msrs_access()
367 msr->fault_expected = false; in guest_test_msrs_access()
368 break; in guest_test_msrs_access()
371 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
372 msr->write = false; in guest_test_msrs_access()
373 msr->fault_expected = true; in guest_test_msrs_access()
374 break; in guest_test_msrs_access()
377 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
378 msr->write = false; in guest_test_msrs_access()
379 msr->fault_expected = false; in guest_test_msrs_access()
380 break; in guest_test_msrs_access()
383 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
384 msr->write = true; in guest_test_msrs_access()
385 msr->write_val = 1; in guest_test_msrs_access()
386 msr->fault_expected = true; in guest_test_msrs_access()
387 break; in guest_test_msrs_access()
390 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
391 msr->write = false; in guest_test_msrs_access()
392 msr->fault_expected = true; in guest_test_msrs_access()
393 break; in guest_test_msrs_access()
396 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
397 msr->write = false; in guest_test_msrs_access()
398 msr->fault_expected = false; in guest_test_msrs_access()
399 break; in guest_test_msrs_access()
401 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
402 msr->write = true; in guest_test_msrs_access()
403 msr->write_val = 1; in guest_test_msrs_access()
404 msr->fault_expected = false; in guest_test_msrs_access()
405 break; in guest_test_msrs_access()
408 msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS; in guest_test_msrs_access()
409 msr->write = true; in guest_test_msrs_access()
410 msr->write_val = 1; in guest_test_msrs_access()
411 msr->fault_expected = true; in guest_test_msrs_access()
412 break; in guest_test_msrs_access()
415 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
416 msr->write = false; in guest_test_msrs_access()
417 msr->fault_expected = true; in guest_test_msrs_access()
418 break; in guest_test_msrs_access()
421 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
422 msr->write = false; in guest_test_msrs_access()
423 msr->fault_expected = false; in guest_test_msrs_access()
424 break; in guest_test_msrs_access()
426 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
427 msr->write = true; in guest_test_msrs_access()
428 msr->write_val = 1; in guest_test_msrs_access()
429 msr->fault_expected = false; in guest_test_msrs_access()
430 break; in guest_test_msrs_access()
433 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
434 msr->write = false; in guest_test_msrs_access()
435 msr->fault_expected = true; in guest_test_msrs_access()
436 break; in guest_test_msrs_access()
440 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
441 msr->write = false; in guest_test_msrs_access()
442 msr->fault_expected = false; in guest_test_msrs_access()
443 break; in guest_test_msrs_access()
445 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
446 msr->write = true; in guest_test_msrs_access()
447 msr->write_val = 0; in guest_test_msrs_access()
448 msr->fault_expected = false; in guest_test_msrs_access()
449 break; in guest_test_msrs_access()
455 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
456 msr->write = false; in guest_test_msrs_access()
457 msr->fault_expected = true; in guest_test_msrs_access()
458 break; in guest_test_msrs_access()
464 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
465 msr->write = false; in guest_test_msrs_access()
466 msr->fault_expected = false; in guest_test_msrs_access()
467 break; in guest_test_msrs_access()
472 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
473 msr->write = true; in guest_test_msrs_access()
474 msr->write_val = 0xdeadbeef; in guest_test_msrs_access()
475 msr->fault_expected = true; in guest_test_msrs_access()
476 break; in guest_test_msrs_access()
481 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
482 msr->write = true; in guest_test_msrs_access()
483 msr->write_val = 1; in guest_test_msrs_access()
484 msr->fault_expected = false; in guest_test_msrs_access()
485 break; in guest_test_msrs_access()
494 memcpy(prev_cpuid, vcpu->cpuid, kvm_cpuid2_size(vcpu->cpuid->nent)); in guest_test_msrs_access()
497 msr->idx, msr->write ? "write" : "read"); in guest_test_msrs_access()
507 break; in guest_test_msrs_access()
546 prev_cpuid = allocate_kvm_cpuid2(vcpu->cpuid->nent); in guest_test_hcalls_access()
554 hcall->control = 0xbeef; in guest_test_hcalls_access()
555 hcall->expect = HV_STATUS_INVALID_HYPERCALL_CODE; in guest_test_hcalls_access()
556 break; in guest_test_hcalls_access()
559 hcall->control = HVCALL_POST_MESSAGE; in guest_test_hcalls_access()
560 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
561 break; in guest_test_hcalls_access()
564 hcall->control = HVCALL_POST_MESSAGE; in guest_test_hcalls_access()
565 hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT; in guest_test_hcalls_access()
566 break; in guest_test_hcalls_access()
569 hcall->control = HVCALL_SIGNAL_EVENT; in guest_test_hcalls_access()
570 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
571 break; in guest_test_hcalls_access()
574 hcall->control = HVCALL_SIGNAL_EVENT; in guest_test_hcalls_access()
575 hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT; in guest_test_hcalls_access()
576 break; in guest_test_hcalls_access()
579 hcall->control = HVCALL_RESET_DEBUG_SESSION; in guest_test_hcalls_access()
580 hcall->expect = HV_STATUS_INVALID_HYPERCALL_CODE; in guest_test_hcalls_access()
581 break; in guest_test_hcalls_access()
584 hcall->control = HVCALL_RESET_DEBUG_SESSION; in guest_test_hcalls_access()
585 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
586 break; in guest_test_hcalls_access()
589 hcall->control = HVCALL_RESET_DEBUG_SESSION; in guest_test_hcalls_access()
590 hcall->expect = HV_STATUS_OPERATION_DENIED; in guest_test_hcalls_access()
591 break; in guest_test_hcalls_access()
594 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE; in guest_test_hcalls_access()
595 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
596 break; in guest_test_hcalls_access()
599 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE; in guest_test_hcalls_access()
600 hcall->expect = HV_STATUS_SUCCESS; in guest_test_hcalls_access()
601 break; in guest_test_hcalls_access()
603 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX; in guest_test_hcalls_access()
604 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
605 break; in guest_test_hcalls_access()
608 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX; in guest_test_hcalls_access()
609 hcall->expect = HV_STATUS_SUCCESS; in guest_test_hcalls_access()
610 break; in guest_test_hcalls_access()
613 hcall->control = HVCALL_SEND_IPI; in guest_test_hcalls_access()
614 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
615 break; in guest_test_hcalls_access()
618 hcall->control = HVCALL_SEND_IPI; in guest_test_hcalls_access()
619 hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT; in guest_test_hcalls_access()
620 break; in guest_test_hcalls_access()
622 /* Nothing in 'sparse banks' -> success */ in guest_test_hcalls_access()
623 hcall->control = HVCALL_SEND_IPI_EX; in guest_test_hcalls_access()
624 hcall->expect = HV_STATUS_SUCCESS; in guest_test_hcalls_access()
625 break; in guest_test_hcalls_access()
628 hcall->control = HVCALL_NOTIFY_LONG_SPIN_WAIT; in guest_test_hcalls_access()
629 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
630 break; in guest_test_hcalls_access()
633 hcall->control = HVCALL_NOTIFY_LONG_SPIN_WAIT; in guest_test_hcalls_access()
634 hcall->expect = HV_STATUS_SUCCESS; in guest_test_hcalls_access()
635 break; in guest_test_hcalls_access()
638 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE | HV_HYPERCALL_FAST_BIT; in guest_test_hcalls_access()
639 hcall->ud_expected = true; in guest_test_hcalls_access()
640 break; in guest_test_hcalls_access()
643 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE | HV_HYPERCALL_FAST_BIT; in guest_test_hcalls_access()
644 hcall->ud_expected = false; in guest_test_hcalls_access()
645 hcall->expect = HV_STATUS_SUCCESS; in guest_test_hcalls_access()
646 break; in guest_test_hcalls_access()
648 hcall->control = HV_EXT_CALL_QUERY_CAPABILITIES; in guest_test_hcalls_access()
649 hcall->expect = HV_STATUS_ACCESS_DENIED; in guest_test_hcalls_access()
650 break; in guest_test_hcalls_access()
653 hcall->control = HV_EXT_CALL_QUERY_CAPABILITIES | HV_HYPERCALL_FAST_BIT; in guest_test_hcalls_access()
654 hcall->expect = HV_STATUS_INVALID_PARAMETER; in guest_test_hcalls_access()
655 break; in guest_test_hcalls_access()
663 memcpy(prev_cpuid, vcpu->cpuid, kvm_cpuid2_size(vcpu->cpuid->nent)); in guest_test_hcalls_access()
665 pr_debug("Stage %d: testing hcall: 0x%lx\n", stage, hcall->control); in guest_test_hcalls_access()
675 break; in guest_test_hcalls_access()
690 pr_info("Testing access to Hyper-V specific MSRs\n"); in main()
693 pr_info("Testing access to Hyper-V hypercalls\n"); in main()