Lines Matching +full:0 +full:x3e0
74 #define HV_SVM_EXITCODE_ENL 0xf0000000
113 u64 avic_backing_page; /* Offset 0xe0 */
114 u8 reserved_6[8]; /* Offset 0xe8 */
115 u64 avic_logical_id; /* Offset 0xf0 */
116 u64 avic_physical_id; /* Offset 0xf8 */
121 * Offset 0x3e0, 32 bytes reserved
131 #define TLB_CONTROL_DO_NOTHING 0
136 #define V_TPR_MASK 0x0f
145 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
159 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
175 #define SVM_VM_CR_VALID_MASK 0x001fULL
176 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
177 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
179 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
249 #define SVM_SELECTOR_TYPE_MASK (0xf)
262 #define INTERCEPT_CR0_READ 0
266 #define INTERCEPT_CR0_WRITE (16 + 0)
271 #define INTERCEPT_DR0_READ 0
279 #define INTERCEPT_DR0_WRITE (16 + 0)
288 #define SVM_EVTINJ_VEC_MASK 0xff
293 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
316 #define SVM_EXITINFO_REG_MASK 0x0F