1 // SPDX-License-Identifier: GPL-2.0
8 /* This file contains sub-register zero extension checks for insns defining
9  * sub-registers, meaning:
10  *   - All insns under BPF_ALU class. Their BPF_ALU32 variants or narrow width
11  *     forms (BPF_END) could define sub-registers.
12  *   - Narrow direct loads, BPF_B/H/W | BPF_LDX.
13  *   - BPF_LD is not exposed to JIT back-ends, so no need for testing.
15  * "get_prandom_u32" is used to initialize low 32-bit of some registers to
16  * prevent potential optimizations done by verifier or JIT back-ends which could
23 __success __success_unpriv __retval(0)
29 	r0 = 0x100000000 ll;				\  in add32_reg_zero_extend_check()
31 	r0 >>= 32;					\  in add32_reg_zero_extend_check()
40 __success __success_unpriv __retval(0)
45 	r1 = 0x1000000000 ll;				\  in add32_imm_zero_extend_check()
47 	/* An insn could have no effect on the low 32-bit, for example:\  in add32_imm_zero_extend_check()
48 	 *   a = a + 0					\  in add32_imm_zero_extend_check()
49 	 *   a = a | 0					\  in add32_imm_zero_extend_check()
50 	 *   a = a & -1					\  in add32_imm_zero_extend_check()
51 	 * But, they should still zero high 32-bit.	\  in add32_imm_zero_extend_check()
53 	w0 += 0;					\  in add32_imm_zero_extend_check()
54 	r0 >>= 32;					\  in add32_imm_zero_extend_check()
57 	r1 = 0x1000000000 ll;				\  in add32_imm_zero_extend_check()
59 	w0 += -2;					\  in add32_imm_zero_extend_check()
60 	r0 >>= 32;					\  in add32_imm_zero_extend_check()
70 __success __success_unpriv __retval(0)
76 	r0 = 0x1ffffffff ll;				\  in sub32_reg_zero_extend_check()
77 	w0 -= w1;					\  in sub32_reg_zero_extend_check()
78 	r0 >>= 32;					\  in sub32_reg_zero_extend_check()
87 __success __success_unpriv __retval(0)
92 	r1 = 0x1000000000 ll;				\  in sub32_imm_zero_extend_check()
94 	w0 -= 0;					\  in sub32_imm_zero_extend_check()
95 	r0 >>= 32;					\  in sub32_imm_zero_extend_check()
98 	r1 = 0x1000000000 ll;				\  in sub32_imm_zero_extend_check()
100 	w0 -= 1;					\  in sub32_imm_zero_extend_check()
101 	r0 >>= 32;					\  in sub32_imm_zero_extend_check()
111 __success __success_unpriv __retval(0)
117 	r0 = 0x100000001 ll;				\  in mul32_reg_zero_extend_check()
119 	r0 >>= 32;					\  in mul32_reg_zero_extend_check()
128 __success __success_unpriv __retval(0)
133 	r1 = 0x1000000000 ll;				\  in mul32_imm_zero_extend_check()
136 	r0 >>= 32;					\  in mul32_imm_zero_extend_check()
139 	r1 = 0x1000000000 ll;				\  in mul32_imm_zero_extend_check()
141 	w0 *= -1;					\  in mul32_imm_zero_extend_check()
142 	r0 >>= 32;					\  in mul32_imm_zero_extend_check()
152 __success __success_unpriv __retval(0)
158 	r0 = -1;					\  in div32_reg_zero_extend_check()
160 	r0 >>= 32;					\  in div32_reg_zero_extend_check()
169 __success __success_unpriv __retval(0)
174 	r1 = 0x1000000000 ll;				\  in div32_imm_zero_extend_check()
177 	r0 >>= 32;					\  in div32_imm_zero_extend_check()
180 	r1 = 0x1000000000 ll;				\  in div32_imm_zero_extend_check()
183 	r0 >>= 32;					\  in div32_imm_zero_extend_check()
193 __success __success_unpriv __retval(0)
199 	r0 = 0x100000001 ll;				\  in or32_reg_zero_extend_check()
201 	r0 >>= 32;					\  in or32_reg_zero_extend_check()
210 __success __success_unpriv __retval(0)
215 	r1 = 0x1000000000 ll;				\  in or32_imm_zero_extend_check()
217 	w0 |= 0;					\  in or32_imm_zero_extend_check()
218 	r0 >>= 32;					\  in or32_imm_zero_extend_check()
221 	r1 = 0x1000000000 ll;				\  in or32_imm_zero_extend_check()
224 	r0 >>= 32;					\  in or32_imm_zero_extend_check()
234 __success __success_unpriv __retval(0)
239 	r1 = 0x100000000 ll;				\  in and32_reg_zero_extend_check()
241 	r0 = 0x1ffffffff ll;				\  in and32_reg_zero_extend_check()
243 	r0 >>= 32;					\  in and32_reg_zero_extend_check()
252 __success __success_unpriv __retval(0)
257 	r1 = 0x1000000000 ll;				\  in and32_imm_zero_extend_check()
259 	w0 &= -1;					\  in and32_imm_zero_extend_check()
260 	r0 >>= 32;					\  in and32_imm_zero_extend_check()
263 	r1 = 0x1000000000 ll;				\  in and32_imm_zero_extend_check()
265 	w0 &= -2;					\  in and32_imm_zero_extend_check()
266 	r0 >>= 32;					\  in and32_imm_zero_extend_check()
276 __success __success_unpriv __retval(0)
281 	r1 = 0x100000000 ll;				\  in lsh32_reg_zero_extend_check()
285 	r0 >>= 32;					\  in lsh32_reg_zero_extend_check()
294 __success __success_unpriv __retval(0)
299 	r1 = 0x1000000000 ll;				\  in lsh32_imm_zero_extend_check()
301 	w0 <<= 0;					\  in lsh32_imm_zero_extend_check()
302 	r0 >>= 32;					\  in lsh32_imm_zero_extend_check()
305 	r1 = 0x1000000000 ll;				\  in lsh32_imm_zero_extend_check()
308 	r0 >>= 32;					\  in lsh32_imm_zero_extend_check()
318 __success __success_unpriv __retval(0)
323 	r1 = 0x1000000000 ll;				\  in rsh32_reg_zero_extend_check()
327 	r0 >>= 32;					\  in rsh32_reg_zero_extend_check()
336 __success __success_unpriv __retval(0)
341 	r1 = 0x1000000000 ll;				\  in rsh32_imm_zero_extend_check()
343 	w0 >>= 0;					\  in rsh32_imm_zero_extend_check()
344 	r0 >>= 32;					\  in rsh32_imm_zero_extend_check()
347 	r1 = 0x1000000000 ll;				\  in rsh32_imm_zero_extend_check()
350 	r0 >>= 32;					\  in rsh32_imm_zero_extend_check()
360 __success __success_unpriv __retval(0)
365 	r1 = 0x1000000000 ll;				\  in neg32_reg_zero_extend_check()
367 	w0 = -w0;					\  in neg32_reg_zero_extend_check()
368 	r0 >>= 32;					\  in neg32_reg_zero_extend_check()
377 __success __success_unpriv __retval(0)
383 	r0 = -1;					\  in mod32_reg_zero_extend_check()
385 	r0 >>= 32;					\  in mod32_reg_zero_extend_check()
394 __success __success_unpriv __retval(0)
399 	r1 = 0x1000000000 ll;				\  in mod32_imm_zero_extend_check()
402 	r0 >>= 32;					\  in mod32_imm_zero_extend_check()
405 	r1 = 0x1000000000 ll;				\  in mod32_imm_zero_extend_check()
408 	r0 >>= 32;					\  in mod32_imm_zero_extend_check()
418 __success __success_unpriv __retval(0)
424 	r0 = 0x100000000 ll;				\  in xor32_reg_zero_extend_check()
426 	r0 >>= 32;					\  in xor32_reg_zero_extend_check()
435 __success __success_unpriv __retval(0)
440 	r1 = 0x1000000000 ll;				\  in xor32_imm_zero_extend_check()
443 	r0 >>= 32;					\  in xor32_imm_zero_extend_check()
452 __success __success_unpriv __retval(0)
457 	r1 = 0x100000000 ll;				\  in mov32_reg_zero_extend_check()
459 	r0 = 0x100000000 ll;				\  in mov32_reg_zero_extend_check()
461 	r0 >>= 32;					\  in mov32_reg_zero_extend_check()
470 __success __success_unpriv __retval(0)
475 	r1 = 0x1000000000 ll;				\  in mov32_imm_zero_extend_check()
477 	w0 = 0;						\  in mov32_imm_zero_extend_check()
478 	r0 >>= 32;					\  in mov32_imm_zero_extend_check()
481 	r1 = 0x1000000000 ll;				\  in mov32_imm_zero_extend_check()
484 	r0 >>= 32;					\  in mov32_imm_zero_extend_check()
494 __success __success_unpriv __retval(0)
499 	r1 = 0x1000000000 ll;				\  in arsh32_reg_zero_extend_check()
503 	r0 >>= 32;					\  in arsh32_reg_zero_extend_check()
512 __success __success_unpriv __retval(0)
517 	r1 = 0x1000000000 ll;				\  in arsh32_imm_zero_extend_check()
519 	w0 s>>= 0;					\  in arsh32_imm_zero_extend_check()
520 	r0 >>= 32;					\  in arsh32_imm_zero_extend_check()
523 	r1 = 0x1000000000 ll;				\  in arsh32_imm_zero_extend_check()
526 	r0 >>= 32;					\  in arsh32_imm_zero_extend_check()
536 __success __success_unpriv __retval(0)
542 	r6 <<= 32;					\  in le_reg_zero_extend_check_1()
546 	r0 >>= 32;					\  in le_reg_zero_extend_check_1()
555 __success __success_unpriv __retval(0)
561 	r6 <<= 32;					\  in le_reg_zero_extend_check_2()
565 	r0 >>= 32;					\  in le_reg_zero_extend_check_2()
574 __success __success_unpriv __retval(0)
580 	r6 <<= 32;					\  in be_reg_zero_extend_check_1()
584 	r0 >>= 32;					\  in be_reg_zero_extend_check_1()
593 __success __success_unpriv __retval(0)
599 	r6 <<= 32;					\  in be_reg_zero_extend_check_2()
603 	r0 >>= 32;					\  in be_reg_zero_extend_check_2()
612 __success __success_unpriv __retval(0)
617 	r6 += -4;					\  in ldx_b_zero_extend_check()
618 	r7 = 0xfaceb00c;				\  in ldx_b_zero_extend_check()
619 	*(u32*)(r6 + 0) = r7;				\  in ldx_b_zero_extend_check()
621 	r1 = 0x1000000000 ll;				\  in ldx_b_zero_extend_check()
623 	r0 = *(u8*)(r6 + 0);				\  in ldx_b_zero_extend_check()
624 	r0 >>= 32;					\  in ldx_b_zero_extend_check()
633 __success __success_unpriv __retval(0)
638 	r6 += -4;					\  in ldx_h_zero_extend_check()
639 	r7 = 0xfaceb00c;				\  in ldx_h_zero_extend_check()
640 	*(u32*)(r6 + 0) = r7;				\  in ldx_h_zero_extend_check()
642 	r1 = 0x1000000000 ll;				\  in ldx_h_zero_extend_check()
644 	r0 = *(u16*)(r6 + 0);				\  in ldx_h_zero_extend_check()
645 	r0 >>= 32;					\  in ldx_h_zero_extend_check()
654 __success __success_unpriv __retval(0)
659 	r6 += -4;					\  in ldx_w_zero_extend_check()
660 	r7 = 0xfaceb00c;				\  in ldx_w_zero_extend_check()
661 	*(u32*)(r6 + 0) = r7;				\  in ldx_w_zero_extend_check()
663 	r1 = 0x1000000000 ll;				\  in ldx_w_zero_extend_check()
665 	r0 = *(u32*)(r6 + 0);				\  in ldx_w_zero_extend_check()
666 	r0 >>= 32;					\  in ldx_w_zero_extend_check()