Lines Matching +full:0 +full:x21

37 	cmp	x2, #0
39 0:	ldrb	w3, [x1], #1
42 	b.ne	0b
56 // bits  7: 0	32-bit lane index
67 0:	str	w3, [x0], #4
70 	b.ne	0b
108 	stp	x0, x1, [sp, #-0x20]!
109 	str	x2, [sp, #0x10]
111 	mov	x5, #0
112 0:	ldrb	w3, [x0, x5]
118 	b.ne	0b
120 1:	ldr	x2, [sp, #0x10]
121 	ldp	x0, x1, [sp], #0x20
158 	// This will reset ZA to all bits 0
188 	mov	x0, #0
190 	svc	#0
212 	mov	x2, #0
215 	svc	#0
231 	mov	x23, #0		// signal count
280 	svc	#0
287 	mov	x22, #0		// generation number, increments per iteration
289 	rdsvl	0, 8
294 0:	mov	x0, x20
295 	sub	x1, x21, #1
298 	subs	x21, x21, #1
299 	b.ne	0b
303 	svc	#0
305 	mrs	x0, S3_3_C4_C2_2	// SVCR should have ZA=1,SM=0
312 0:	sub	x0, x24, x21
314 	subs	x21, x21, #1
315 	bne	0b
321 	mov	x0, #0
324 	svc	#0
329 //	ldr	w0, =0xdeadc0de
331 //	svc	#0
348 	mov	x0, x21
364 	svc	#0
366 //	ldr	w0, =0xdeadc0de
368 //	svc	#0
372 	svc	#0
375 //	svc	#0
387 	svc	#0
399 	svc	#0