Lines Matching +full:a +full:- +full:za +full:- +full:z

1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2015-2019 ARM Limited.
9 // for x in `seq 1 NR_CPUS`; do sve-test & pids=$pids\ $! ; done
15 #include "asm-offsets.h"
16 #include "sme-inst.h"
25 	ldr	z\zt, [x\xn]
29 	str	z\zt, [x\xn]
44 // All clobber x0-x2
64 // Generate a test pattern for storage in SVE registers
69 // These values are used to constuct a 32-bit pattern that is repeated in the
72 // bits 27:22	32-bit lane index
91 // Get the address of shadow data for SVE Z-register Z<xn>
98 // Get the address of shadow data for SVE P-register P<xn - NZR>
107 // Set up test pattern in a SVE Z-register
128 // Set up test pattern in a SVE P-register
153 // We need to generate a canonical FFR value, which consists of a number of
154 // low "1" bits, followed by a number of zeros. This gives us 17 unique values
155 // per 16 bits of FFR, so we create a 4 bit signature out of the PID and
191 // Clobbers x0-x5.
195 	stp	x0, x1, [sp, #-0x20]!
214 // Verify that a SVE Z-register matches its shadow in memory, else abort
216 // Clobbers x0-x7.
239 // Verify that a SVE P-register matches its shadow in memory, else abort
241 // Clobbers x0-x7.
265 // Beware -- corrupts P0.
266 // Clobbers x0-x5.
301 	// Corrupt some random Z-regs
346 // Clobbers x0-x6,x8
348 	str	x30, [sp, #-((sa_sz + 15) / 16 * 16 + 16)]!
410 	// Sanity-check and report the vector length
417 	tst	x19, #(8 - 1)
450 	mov	x21, #0		// Set up Z-regs & shadow with test pattern
464 0:	mov	x0, x20		// Set up P-regs & shadow with test pattern
477 	mrs	x0, S3_3_C4_C2_2	// SVCR should have ZA=0,SM=1