Lines Matching +full:static +full:- +full:trace +full:- +full:id

1 /* SPDX-License-Identifier: GPL-2.0 */
24 	/* PMU->type (32 bit), total # of CPUs (32 bit) */
40  * CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values
49 	/* Number of trace config params in following ETM specific block */
65 /* define fixed version 0 length - allow new format reader to read old files. */
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
83 /* define fixed version 0 length - allow new format reader to read old files. */
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
106  * Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
107  * then IDs are present in the hardware ID packet in the data file.
109 #define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70))  argument
113  * See Embedded Trace Macrocell specification (ARM IHI 0014Q)
114  * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
135  * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
136  * table 6-12 Possible values for the TYPE field in an Exception instruction
137  * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
192  * When working with per-thread scenarios the process under trace can
206 	u64 cs_timestamp; /* Timestamp from trace data, converted to ns if possible */
227 #define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \
228 			  sizeof(((struct perf_record_auxtrace_info *)0)->reserved__))
230 /* CoreSight trace ID is currently the bottom 7 bits of the value */
258 static inline int
262 	pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n");  in cs_etm__process_auxtrace_info_full()
263 	return -1;  in cs_etm__process_auxtrace_info_full()