Lines Matching full:000
22 /* offset=0 */ "tool\000"
23 /* offset=5 */ "duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00…
24 /* offset=78 */ "user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\0…
25 /* offset=145 */ "system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\00…
26 /* offset=210 */ "has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\…
27 …000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated…
28 …et=425 */ "num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a …
29 …"num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs o…
30 /* offset=639 */ "num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\…
31 /* offset=712 */ "num_packages\000tool\000Number of packages. Each package has 1 or more die\000con…
32 …=795 */ "slots\000tool\000Number of functional units that in parallel can execute parts of an inst…
33 …t=902 */ "smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherw…
34 …=1006 */ "system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\00…
35 /* offset=1102 */ "default_core\000"
36 /* offset=1115 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000"
37 /* offset=1174 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000"
38 …et=1233 */ "l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable …
39 … */ "segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,u…
40 …locked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9…
41 …/ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000e…
42 /* offset=1672 */ "hisi_sccl,ddrc\000"
43 …1687 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC …
44 /* offset=1773 */ "uncore_cbox\000"
45 …000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000e…
46 /* offset=2016 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPH…
47 /* offset=2081 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_…
48 /* offset=2152 */ "hisi_sccl,l3c\000"
49 …t=2166 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total…
50 /* offset=2246 */ "uncore_imc_free_running\000"
51 …"uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Tot…
52 /* offset=2365 */ "uncore_imc\000"
53 …offset=2376 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Tot…
54 /* offset=2454 */ "uncore_sys_ddr_pmu\000"
55 … offset=2473 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\…
56 /* offset=2546 */ "uncore_sys_ccn_pmu\000"
57 … offset=2565 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01…
58 /* offset=2639 */ "uncore_sys_cmn_pmu\000"
59 …che_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=…
60 /* offset=2798 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000"
61 /* offset=2820 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\…
62 …000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one…
63 /* offset=3049 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\0…
64 /* offset=3113 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\00…
65 /* offset=3180 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\…
66 …251 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit…
67 …l_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss…
68 /* offset=3479 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000…
69 /* offset=3543 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000…
70 /* offset=3611 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\0…
71 /* offset=3681 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000"
72 /* offset=3703 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000"
73 /* offset=3725 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000"
74 /* offset=3745 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\…
78 { 5 }, /* duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00000\00…
79 { 210 }, /* has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\00000\…
80 …000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated…
81 … 425 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a …
82 … num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs o…
83 { 639 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\00000\…
84 { 712 }, /* num_packages\000tool\000Number of packages. Each package has 1 or more die\000config=9\…
85 …95 }, /* slots\000tool\000Number of functional units that in parallel can execute parts of an inst…
86 …902 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherw…
87 { 145 }, /* system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000 …
88 …006 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\00…
89 { 78 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000…
97 .pmu_name = { 0 /* tool\000 */ },
102 { 1115 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000 */
103 { 1174 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000 */
104 …locked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9…
105 …/* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000e…
106 … 1233 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable …
107 …, /* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,u…
110 …87 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC …
113 …2166 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total…
116 { 2016 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000…
117 { 2081 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HY…
118 …000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000e…
121 { 2376 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total c…
124 … uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Tot…
132 .pmu_name = { 1102 /* default_core\000 */ },
137 .pmu_name = { 1672 /* hisi_sccl,ddrc\000 */ },
142 .pmu_name = { 2152 /* hisi_sccl,l3c\000 */ },
147 .pmu_name = { 1773 /* uncore_cbox\000 */ },
152 .pmu_name = { 2365 /* uncore_imc\000 */ },
157 .pmu_name = { 2246 /* uncore_imc_free_running\000 */ },
162 { 2798 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */
163 { 3479 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\0…
164 …1 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit…
165 …l_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss…
166 { 3543 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\0…
167 { 3611 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000…
168 …000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one…
169 { 2820 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\00…
170 { 3745 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\00…
171 { 3681 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */
172 { 3703 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */
173 { 3725 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */
174 { 3180 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\00…
175 { 3049 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000…
176 { 3113 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\…
184 .pmu_name = { 1102 /* default_core\000 */ },
189 { 2565 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\0000…
192 …che_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=…
195 { 2473 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000…
203 .pmu_name = { 2546 /* uncore_sys_ccn_pmu\000 */ },
208 .pmu_name = { 2639 /* uncore_sys_cmn_pmu\000 */ },
213 .pmu_name = { 2454 /* uncore_sys_ddr_pmu\000 */ },