Lines Matching +full:instruction +full:- +full:fetch
7 … times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs …
12 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
16 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
36 …op-cache that holds translations of previously fetched instructions that were decoded by the legac…
48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
60 … (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose…
72 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
77 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
84 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
89 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
96 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
108 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
113 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
120 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
125 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
132 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
137 "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
144 …er an interval where the front-end delivered no uops for a period of at least 2 cycles which was n…
149 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
156 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
161 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
168 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
173 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
180 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
185 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
192 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
197 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
204 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
209 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
216 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
221 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
228 …tions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this…
245 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This …
249 …"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction ca…
254 …"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts…
258 …"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I)…
263 …"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Count…
267 …PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I)…
272 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [T…
276 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
281 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This …
285 …"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction ca…
290 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [T…
294 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
304 …"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue …
314 …the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (I…
319 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
323 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
333 …"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Qu…
343 …the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (I…
348 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
352 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
362 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
382 …he total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops wil…
391 … of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline wh…
401 …en no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline wh…
406 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
412 …er of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline wh…