Lines Matching +full:back +full:- +full:end

7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
45 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
57 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
98         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
105 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
110 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
117 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
122 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
129 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
134         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
141 … an interval where the front-end delivered no uops for a period of at least 2 cycles which was not…
146 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
153 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
158 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
165 …e delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycle…
170 …fter an interval where the front-end delivered no uops for a period of 32 cycles which was not int…
177 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
182 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
189 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
194 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
201 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
206 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
213 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
218 …after an interval where the front-end delivered no uops for a period of 8 cycles which was not int…
225 …ctions that are delivered to the back-end after a front-end stall of at least 8 cycles. During thi…
384 …ed to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
394 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
399 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
405 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
414 …ed to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
424 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
429 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
435 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…