Lines Matching +full:per +full:- +full:queue

11         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
29 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
52 …counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Dec…
62 …t counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Dec…
72 …counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MIT…
82 …nt counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MIT…
87 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
92 …counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Dec…
97 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
101 …n": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Dec…
106         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
110 …queue is empty and can indicate that the application may be bound in the front end.  It does not d…
115         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
119 …n": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MIT…
124 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
129 …counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MIT…
134         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
138 …n": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MIT…
143 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while …
148 …counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Mi…
153 …d by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microc…
158 …d by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Mi…
163 …"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffe…
169 …ption": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by…
174 …Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microc…
178 …Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Mi…
183 …"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while …
187 … the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Mi…
202 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (M…
206 …his event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Mi…
211 …"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend…
215 …per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode …
220 …"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocatio…
225 …"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivere…
240 …"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocatio…
245 …"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is  …