Lines Matching +full:software +full:- +full:generated

5 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
41 …"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.…
65     "BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.",
71     "BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.",
89 … requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2…
131 …he requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2…
173 …refetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware…
179 …refetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data har…
185 …refetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and…
191 …the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware…
197 …the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data har…
203 …the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and…
209 …d by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware…
215 …d by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data har…
221 …d by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and…