Lines Matching +full:instruction +full:- +full:fetch

5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
161 …eculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
173 …ption": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH…
179 …ption": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH…
185 …"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core fo…
287 …"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations eac…
292 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
316     "BriefDescription": "L2 cache requests: instruction cache reads.",
358 …": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request m…
364 … to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiabl…
370 …": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modif…
376 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache h…
382 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache a…
394 …n": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
406 …he requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2…
430 …ion": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
442 …n": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
448 …s accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequent…
454 …accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into…
460 …s accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previo…
466 …y the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequent…
472 …s accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines i…
478 …s accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequent…
484 …s accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines i…
490 …t in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for …
502 …ipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequent…
508 …eline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into…
514 …ipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previo…
520 …h miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequent…
526 …ipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines i…
532 …ipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequent…
538 …ipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines i…
544 …t in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for …
556 … by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequent…
562 …y the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into…
568 … by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previo…
574 …ipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequent…
580 … by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines i…
586 … by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequent…
592 … by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines i…
598 …and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for …
610     "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
615 …"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another ca…
620     "BriefDescription": "Instruction cache hits.",
626     "BriefDescription": "Instruction cache misses.",
632     "BriefDescription": "Instruction cache accesses of all types.",