Lines Matching +full:non +full:- +full:prefetch

5 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft…
11     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
82 …BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-c…
88 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
94     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
100     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
148 …re to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modi…
154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
172 …e to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-mod…
178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
184 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
190 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
196 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
208     "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.",
226 …etch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cachea…
257 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
263 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
269 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
275 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
281 … instruction stream was being modified by another processor in an MP system - typically a highly u…
298 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
304 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
310 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
346     "BriefDescription": "All Op Cache accesses. Counts Op Cache micro-tag hit/miss events",
352     "BriefDescription": "Op Cache Miss. Counts Op Cache micro-tag hit/miss events",
358     "BriefDescription": "Op Cache Hit. Counts Op Cache micro-tag hit/miss events",