Lines Matching +full:instruction +full:- +full:fetch

5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11     "BriefDescription": "Branch Instruction Finished",
23     "BriefDescription": "Branch Instruction completed",
47     "BriefDescription": "Number of I-ERAT reloads",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
101 …The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group…
102 …s Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due…
107 …The processor's Instruction cache was reloaded from another chip's memory on the same Node or Grou…
108 …s Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) du…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …ion": "The processor's Instruction cache was reloaded from local core's L2 due to either an instru…
119 …tion": "The processor's Instruction cache was reloaded from a location other than the local core's…
120 …ocessor's Instruction cache was reloaded from a location other than the local core's L2 due to eit…
125 …on": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conf…
126 …essor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to ei…
131 …ption": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflic…
132 …rocessor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to eithe…
137 …e processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts o…
138 …Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. …
143 …cription": "The processor's Instruction cache was reloaded from local core's L2 without conflict d…
144 …e processor's Instruction cache was reloaded from local core's L2 without conflict due to either a…
149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an…
150 …ion": "The processor's Instruction cache was reloaded from local core's L3 due to either an instru…
155     "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
161 …tion": "The processor's Instruction cache was reloaded from a location other than the local core's…
162 …ocessor's Instruction cache was reloaded from a location other than the local core's L3 due to eit…
167 …ption": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflic…
168 …rocessor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to eithe…
173 …e processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit o…
174 …Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. …
179 …cription": "The processor's Instruction cache was reloaded from local core's L3 without conflict d…
180 …e processor's Instruction cache was reloaded from local core's L3 without conflict due to either a…
185 …fDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due …
186 … "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an i…
191 …efDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due t…
192 …: "The processor's Instruction cache was reloaded from the local chip's Memory due to either an in…
197 …he processor's Instruction cache was reloaded from a memory location including L4 from local remot…
198 … Instruction cache was reloaded from a memory location including L4 from local remote or distant d…
203 …Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a diffe…
204 …Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a diffe…
209 …ocessor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 …
210 …Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the sam…
215 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod…
216 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod…
221 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node …
222 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node …
227 … "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group …
228 …r's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due …
233 …The processor's Instruction cache was reloaded from another chip's memory on the same Node or Grou…
234 …s Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) du…
239 …tion": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch",
240 …al and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch"
245 … Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch",
251 …"Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
252 …Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch"
263 …Description": "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
264 …icDescription": "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch"
269 …BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch",
270 …"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch"
275 …ion": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
276 …l and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch"
281 …or the original scope was System and it should have been smaller. Counts for an instruction fetch",
287 …Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
288 …get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch"
293 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
299 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
305 …B from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
311 … from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
317 …A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
323 …ded into the TLB from a location other than the local core's L2 due to a instruction side request",
329 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
335 …y was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
341 …A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
347 …ded into the TLB from a location other than the local core's L3 due to a instruction side request",
353 …loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
359 …m local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
365 …y was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
371 …le Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
377 …able Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
383 …rom a memory location including L4 from local remote or distant due to a instruction side request",
389 …om another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
395 …red or modified data from another core's L2/L3 on the same chip due to a instruction side request",
401 …hip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
407 …hip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
413 … TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
419 … from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",