Lines Matching +full:9 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
112 /* Register-based PAN access, for save/restore purposes */
167 #include "asm/sysreg-defs.h"
184 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
186 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
187 #define OSLSR_EL1_OSLK BIT(1)
192 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
201 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
203 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
205 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
206 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
208 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
209 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
210 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
276 #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
328 #define SYS_PAR_EL1_F BIT(0)
331 #define SYS_PAR_EL1_PTW BIT(8)
332 #define SYS_PAR_EL1_S BIT(9)
333 #define SYS_PAR_EL1_AssuredOnly BIT(12)
334 #define SYS_PAR_EL1_TopLevel BIT(13)
335 #define SYS_PAR_EL1_Overlay BIT(14)
336 #define SYS_PAR_EL1_DirtyBit BIT(15)
338 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
339 #define SYS_PAR_EL1_RES1 BIT(11)
342 #define SYS_PAR_EL1_NS BIT(9)
343 #define SYS_PAR_EL1_F0_IMPDEF BIT(10)
344 #define SYS_PAR_EL1_NSE BIT(11)
372 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
373 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
375 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
392 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
420 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
421 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
422 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
423 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
424 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
425 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
426 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
427 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
428 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
429 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
430 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
431 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
455 * n: 0-15
461 * n: 0-15
553 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
559 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
609 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
627 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
651 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
652 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
653 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
660 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
669 #define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
671 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
672 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
673 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
674 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
675 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
676 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
677 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
678 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
710 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
711 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
712 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
713 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
714 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
715 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
716 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
717 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
718 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
719 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
720 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
721 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
722 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
723 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
724 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
725 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
726 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
727 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
728 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
729 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
730 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
731 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
732 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
733 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
734 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
735 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
736 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
737 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
738 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
739 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
773 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
774 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
775 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
776 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
777 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
778 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
779 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
780 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
781 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
782 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
783 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
784 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
785 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
786 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
787 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
788 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
789 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
790 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
791 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
792 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
793 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
794 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
795 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
796 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
797 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
798 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
799 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
800 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
801 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
802 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
803 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
804 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
805 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
821 #define SCTLR_ELx_ENTP2 (BIT(60))
822 #define SCTLR_ELx_DSSBS (BIT(44))
823 #define SCTLR_ELx_ATA (BIT(43))
828 #define SCTLR_ELx_ITFSB (BIT(37))
829 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
830 #define SCTLR_ELx_ENIB (BIT(30))
831 #define SCTLR_ELx_LSMAOE (BIT(29))
832 #define SCTLR_ELx_nTLSMD (BIT(28))
833 #define SCTLR_ELx_ENDA (BIT(27))
834 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
835 #define SCTLR_ELx_EIS (BIT(22))
836 #define SCTLR_ELx_IESB (BIT(21))
837 #define SCTLR_ELx_TSCXT (BIT(20))
838 #define SCTLR_ELx_WXN (BIT(19))
839 #define SCTLR_ELx_ENDB (BIT(13))
840 #define SCTLR_ELx_I (BIT(12))
841 #define SCTLR_ELx_EOS (BIT(11))
842 #define SCTLR_ELx_SA (BIT(3))
843 #define SCTLR_ELx_C (BIT(2))
844 #define SCTLR_ELx_A (BIT(1))
845 #define SCTLR_ELx_M (BIT(0))
848 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
849 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
850 (BIT(29)))
852 #define SCTLR_EL2_BT (BIT(36))
941 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
942 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
944 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
945 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
947 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
948 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
951 #define SYS_GCR_EL1_RRND (BIT(16))
957 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
974 /* TFSR{,E0}_EL1 bit definitions */
981 #define SYS_MPIDR_SAFE_VAL (BIT(31))
984 /* ICH_MISR_EL2 bit definitions */
988 /* ICH_LR*_EL2 bit definitions */
989 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1002 /* ICH_HCR_EL2 bit definitions */
1013 /* ICH_VMCR_EL2 bit definitions */
1020 #define ICH_VMCR_EOIM_SHIFT 9
1033 /* ICH_VTR_EL2 bit definitions */
1173 * set mask are set. Other bits are left as-is.