Lines Matching +full:8 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
34 #define CRm_shift 8
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
112 /* Register-based PAN access, for save/restore purposes */
167 #include "asm/sysreg-defs.h"
191 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
200 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
201 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
202 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
203 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
204 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
205 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
206 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
208 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
209 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
210 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
230 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
276 #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
331 #define SYS_PAR_EL1_PTW BIT(8)
332 #define SYS_PAR_EL1_S BIT(9)
341 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
342 #define SYS_PAR_EL1_NS BIT(9)
351 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
372 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
373 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
375 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
383 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
384 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
385 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
386 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
387 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
392 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
420 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
421 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
422 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
423 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
424 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
425 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
426 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
427 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
428 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
429 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
430 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
431 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
455 * n: 0-15
461 * n: 0-15
492 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
547 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
553 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
559 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
609 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
627 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
647 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
648 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
649 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
650 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
651 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
652 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
653 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
654 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
655 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
656 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
657 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
658 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
659 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
660 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
668 #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
669 #define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
671 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
672 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
673 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
674 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
675 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
676 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
677 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
678 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
680 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
681 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
682 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
683 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
684 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
685 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
686 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
687 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
688 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
689 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
690 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
691 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
692 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
693 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
694 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
695 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
696 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
697 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
698 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
699 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
700 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
701 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
702 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
703 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
704 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
705 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
706 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
707 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
708 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
709 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
710 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
711 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
712 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
713 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
714 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
715 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
716 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
717 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
718 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
719 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
720 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
721 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
722 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
723 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
724 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
725 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
726 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
727 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
728 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
729 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
730 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
731 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
732 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
733 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
734 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
735 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
736 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
737 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
738 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
739 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
740 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
741 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
742 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
743 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
744 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
745 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
746 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
747 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
748 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
749 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
750 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
751 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
752 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
753 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
754 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
755 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
756 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
757 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
758 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
759 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
760 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
761 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
762 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
763 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
764 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
765 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
766 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
767 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
768 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
769 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
770 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
771 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
772 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
773 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
774 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
775 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
776 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
777 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
778 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
779 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
780 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
781 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
782 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
783 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
784 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
785 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
786 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
787 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
788 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
789 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
790 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
791 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
792 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
793 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
794 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
795 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
796 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
797 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
798 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
799 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
800 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
801 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
802 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
803 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
804 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
805 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
896 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
957 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
971 #define SYS_RGSR_EL1_SEED_SHIFT 8
989 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1020 #define ICH_VMCR_EOIM_SHIFT 9
1173 * set mask are set. Other bits are left as-is.