Lines Matching +full:- +full:1 +full:ul
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - ARM Ltd
12 #define ESR_ELx_EC_UNKNOWN UL(0x00)
13 #define ESR_ELx_EC_WFx UL(0x01)
15 #define ESR_ELx_EC_CP15_32 UL(0x03)
16 #define ESR_ELx_EC_CP15_64 UL(0x04)
17 #define ESR_ELx_EC_CP14_MR UL(0x05)
18 #define ESR_ELx_EC_CP14_LS UL(0x06)
19 #define ESR_ELx_EC_FP_ASIMD UL(0x07)
20 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
21 #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
22 /* Unallocated EC: 0x0A - 0x0B */
23 #define ESR_ELx_EC_CP14_64 UL(0x0C)
24 #define ESR_ELx_EC_BTI UL(0x0D)
25 #define ESR_ELx_EC_ILL UL(0x0E)
26 /* Unallocated EC: 0x0F - 0x10 */
27 #define ESR_ELx_EC_SVC32 UL(0x11)
28 #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
29 #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
31 #define ESR_ELx_EC_SVC64 UL(0x15)
32 #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
33 #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
34 #define ESR_ELx_EC_SYS64 UL(0x18)
35 #define ESR_ELx_EC_SVE UL(0x19)
36 #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
38 #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
39 #define ESR_ELx_EC_SME UL(0x1D)
41 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
42 #define ESR_ELx_EC_IABT_LOW UL(0x20)
43 #define ESR_ELx_EC_IABT_CUR UL(0x21)
44 #define ESR_ELx_EC_PC_ALIGN UL(0x22)
46 #define ESR_ELx_EC_DABT_LOW UL(0x24)
47 #define ESR_ELx_EC_DABT_CUR UL(0x25)
48 #define ESR_ELx_EC_SP_ALIGN UL(0x26)
49 #define ESR_ELx_EC_MOPS UL(0x27)
50 #define ESR_ELx_EC_FP_EXC32 UL(0x28)
51 /* Unallocated EC: 0x29 - 0x2B */
52 #define ESR_ELx_EC_FP_EXC64 UL(0x2C)
53 /* Unallocated EC: 0x2D - 0x2E */
54 #define ESR_ELx_EC_SERROR UL(0x2F)
55 #define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
56 #define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
57 #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
58 #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
59 #define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
60 #define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
61 /* Unallocated EC: 0x36 - 0x37 */
62 #define ESR_ELx_EC_BKPT32 UL(0x38)
64 #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
66 #define ESR_ELx_EC_BRK64 UL(0x3C)
67 /* Unallocated EC: 0x3D - 0x3F */
68 #define ESR_ELx_EC_MAX UL(0x3F)
72 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
76 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
85 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
89 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
91 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
93 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
101 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
103 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
105 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
107 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
133 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
135 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
137 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
139 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
141 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
143 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
145 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
149 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
151 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
153 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
155 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
157 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
164 #define ESR_ELx_CV (UL(1) << 24)
166 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
167 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
168 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
169 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
170 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
171 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
172 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
173 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
175 #define DISR_EL1_IDS (UL(1) << 24)
193 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
199 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
200 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
201 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
203 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
205 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
207 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
209 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
229 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
244 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
249 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
259 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
300 * ISS field definitions for floating-point exception traps
306 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
316 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
317 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
318 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
320 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
322 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
324 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
342 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
345 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
348 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
349 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
350 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
360 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
374 #define ESR_ELx_SME_ISS_ILL 1
380 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
381 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
382 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
383 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
384 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
385 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
386 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
415 (esr == ESR_ELx_FSC_FAULT_L(1)) || in esr_fsc_is_translation_fault()
417 (esr == ESR_ELx_FSC_FAULT_L(-1)); in esr_fsc_is_translation_fault()
426 (esr == ESR_ELx_FSC_PERM_L(1)) || in esr_fsc_is_permission_fault()
436 (esr == ESR_ELx_FSC_ACCESS_L(1)) || in esr_fsc_is_access_flag_fault()
446 /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */