109 		if (asrc->lane[id].ratio_source !=  in tegra186_asrc_runtime_resume()
116 			asrc->lane[id].int_part);  in tegra186_asrc_runtime_resume()
121 			asrc->lane[id].frac_part);  in tegra186_asrc_runtime_resume()
173 		     asrc->lane[id].input_thresh);  in tegra186_asrc_in_hw_params()
196 		     asrc->lane[id].output_thresh);  in tegra186_asrc_out_hw_params()
206 	if (asrc->lane[id].hwcomp_disable) {  in tegra186_asrc_out_hw_params()
225 			   1, asrc->lane[id].ratio_source);  in tegra186_asrc_out_hw_params()
227 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) {  in tegra186_asrc_out_hw_params()
230 			asrc->lane[id].int_part);  in tegra186_asrc_out_hw_params()
233 			asrc->lane[id].frac_part);  in tegra186_asrc_out_hw_params()
249 	ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source;  in tegra186_asrc_get_ratio_source()
264 	asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0];  in tegra186_asrc_put_ratio_source()
268 				 asrc->lane[id].ratio_source,  in tegra186_asrc_put_ratio_source()
285 		    &asrc->lane[id].int_part);  in tegra186_asrc_get_ratio_int()
287 	ucontrol->value.integer.value[0] = asrc->lane[id].int_part;  in tegra186_asrc_get_ratio_int()
302 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {  in tegra186_asrc_put_ratio_int()
304 			"Lane %d ratio source is ARAD, invalid SW update\n",  in tegra186_asrc_put_ratio_int()
309 	asrc->lane[id].int_part = ucontrol->value.integer.value[0];  in tegra186_asrc_put_ratio_int()
315 				 asrc->lane[id].int_part, &change);  in tegra186_asrc_put_ratio_int()
333 		    &asrc->lane[id].frac_part);  in tegra186_asrc_get_ratio_frac()
335 	ucontrol->value.integer.value[0] = asrc->lane[id].frac_part;  in tegra186_asrc_get_ratio_frac()
350 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {  in tegra186_asrc_put_ratio_frac()
352 			"Lane %d ratio source is ARAD, invalid SW update\n",  in tegra186_asrc_put_ratio_frac()
357 	asrc->lane[id].frac_part = ucontrol->value.integer.value[0];  in tegra186_asrc_put_ratio_frac()
363 				 asrc->lane[id].frac_part, &change);  in tegra186_asrc_put_ratio_frac()
379 	ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable;  in tegra186_asrc_get_hwcomp_disable()
394 	if (value == asrc->lane[id].hwcomp_disable)  in tegra186_asrc_put_hwcomp_disable()
397 	asrc->lane[id].hwcomp_disable = value;  in tegra186_asrc_put_hwcomp_disable()
411 	ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3);  in tegra186_asrc_get_input_threshold()
424 	int value = (asrc->lane[id].input_thresh & ~(0x3)) |  in tegra186_asrc_put_input_threshold()
427 	if (value == asrc->lane[id].input_thresh)  in tegra186_asrc_put_input_threshold()
430 	asrc->lane[id].input_thresh = value;  in tegra186_asrc_put_input_threshold()
444 	ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3);  in tegra186_asrc_get_output_threshold()
457 	int value = (asrc->lane[id].output_thresh & ~(0x3)) |  in tegra186_asrc_put_output_threshold()
460 	if (value == asrc->lane[id].output_thresh)  in tegra186_asrc_put_output_threshold()
463 	asrc->lane[id].output_thresh = value;  in tegra186_asrc_put_output_threshold()
995 		asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW;  in tegra186_asrc_platform_probe()
996 		asrc->lane[i].int_part = 1;  in tegra186_asrc_platform_probe()
997 		asrc->lane[i].frac_part = 0;  in tegra186_asrc_platform_probe()
998 		asrc->lane[i].hwcomp_disable = 0;  in tegra186_asrc_platform_probe()
999 		asrc->lane[i].input_thresh =  in tegra186_asrc_platform_probe()
1001 		asrc->lane[i].output_thresh =  in tegra186_asrc_platform_probe()