Lines Matching +full:dsp +full:- +full:irq
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
15 * Hardware interface for generic Intel audio DSP HDA IP
32 * tell DSP cmd is done - clear busy in hda_dsp_ipc_host_done()
33 * interrupt and send reply msg to dsp in hda_dsp_ipc_host_done()
50 * set DONE bit - tell DSP we have received the reply msg in hda_dsp_ipc_dsp_done()
51 * from DSP, and processed it, don't send more reply to host in hda_dsp_ipc_dsp_done()
67 /* send IPC message to DSP */ in hda_dsp_ipc_send_msg()
68 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, in hda_dsp_ipc_send_msg()
69 msg->msg_size); in hda_dsp_ipc_send_msg()
93 struct sof_ipc4_msg *msg_data = msg->msg_data; in hda_dsp_ipc4_schedule_d0i3_work()
95 /* Schedule a delayed work for d0i3 entry after sending non-pm ipc msg */ in hda_dsp_ipc4_schedule_d0i3_work()
96 if (hda_dsp_ipc4_pm_msg(msg_data->primary)) in hda_dsp_ipc4_schedule_d0i3_work()
99 mod_delayed_work(system_wq, &hdev->d0i3_work, in hda_dsp_ipc4_schedule_d0i3_work()
106 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; in hda_dsp_ipc4_send_msg()
107 struct sof_ipc4_msg *msg_data = msg->msg_data; in hda_dsp_ipc4_send_msg()
110 hdev->delayed_ipc_tx_msg = msg; in hda_dsp_ipc4_send_msg()
114 hdev->delayed_ipc_tx_msg = NULL; in hda_dsp_ipc4_send_msg()
117 if (msg_data->data_size) in hda_dsp_ipc4_send_msg()
118 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, in hda_dsp_ipc4_send_msg()
119 msg_data->data_size); in hda_dsp_ipc4_send_msg()
121 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE, msg_data->extension); in hda_dsp_ipc4_send_msg()
123 msg_data->primary | HDA_DSP_REG_HIPCI_BUSY); in hda_dsp_ipc4_send_msg()
133 struct snd_sof_ipc_msg *msg = sdev->msg; in hda_dsp_ipc_get_reply()
143 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); in hda_dsp_ipc_get_reply()
147 hdr = msg->msg_data; in hda_dsp_ipc_get_reply()
148 if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) || in hda_dsp_ipc_get_reply()
149 hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) { in hda_dsp_ipc_get_reply()
158 memcpy(msg->reply_data, &reply, sizeof(reply)); in hda_dsp_ipc_get_reply()
160 msg->reply_error = 0; in hda_dsp_ipc_get_reply()
167 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context) in hda_dsp_ipc4_irq_thread() argument
179 /* DSP received the message */ in hda_dsp_ipc4_irq_thread()
189 /* Message from DSP (reply or notification) */ in hda_dsp_ipc4_irq_thread()
201 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { in hda_dsp_ipc4_irq_thread()
202 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; in hda_dsp_ipc4_irq_thread()
204 data->primary = primary; in hda_dsp_ipc4_irq_thread()
205 data->extension = extension; in hda_dsp_ipc4_irq_thread()
207 spin_lock_irq(&sdev->ipc_lock); in hda_dsp_ipc4_irq_thread()
211 snd_sof_ipc_reply(sdev, data->primary); in hda_dsp_ipc4_irq_thread()
213 spin_unlock_irq(&sdev->ipc_lock); in hda_dsp_ipc4_irq_thread()
215 dev_dbg_ratelimited(sdev->dev, in hda_dsp_ipc4_irq_thread()
224 sdev->ipc->msg.rx_data = ¬ification_data; in hda_dsp_ipc4_irq_thread()
226 sdev->ipc->msg.rx_data = NULL; in hda_dsp_ipc4_irq_thread()
228 /* Let DSP know that we have finished processing the message */ in hda_dsp_ipc4_irq_thread()
237 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); in hda_dsp_ipc4_irq_thread()
240 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; in hda_dsp_ipc4_irq_thread()
242 if (hdev->delayed_ipc_tx_msg) in hda_dsp_ipc4_irq_thread()
243 hda_dsp_ipc4_send_msg(sdev, hdev->delayed_ipc_tx_msg); in hda_dsp_ipc4_irq_thread()
251 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context) in hda_dsp_ipc_irq_thread() argument
269 /* is this a reply message from the DSP */ in hda_dsp_ipc_irq_thread()
283 * waking up the sender and re-enabling the interrupt. Also in hda_dsp_ipc_irq_thread()
285 * if the DSP is fast enough to receive an IPC message, reply to in hda_dsp_ipc_irq_thread()
291 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { in hda_dsp_ipc_irq_thread()
292 spin_lock_irq(&sdev->ipc_lock); in hda_dsp_ipc_irq_thread()
294 /* handle immediate reply from DSP core */ in hda_dsp_ipc_irq_thread()
301 spin_unlock_irq(&sdev->ipc_lock); in hda_dsp_ipc_irq_thread()
303 dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n", in hda_dsp_ipc_irq_thread()
310 /* is this a new message from DSP */ in hda_dsp_ipc_irq_thread()
322 /* handle messages from DSP */ in hda_dsp_ipc_irq_thread()
324 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_ipc_irq_thread()
332 * to false as the DSP might be able to boot in the next in hda_dsp_ipc_irq_thread()
335 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS && in hda_dsp_ipc_irq_thread()
336 hda->boot_iteration < HDA_FW_BOOT_ATTEMPTS) in hda_dsp_ipc_irq_thread()
342 /* normal message - process normally */ in hda_dsp_ipc_irq_thread()
355 dev_dbg_ratelimited(sdev->dev, in hda_dsp_ipc_irq_thread()
356 "nothing to do in IPC IRQ thread\n"); in hda_dsp_ipc_irq_thread()
363 /* Check if an IPC IRQ occurred */
366 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_check_ipc_irq()
370 if (sdev->dspless_mode_selected) in hda_dsp_check_ipc_irq()
387 hda->code_loading = 0; in hda_dsp_check_ipc_irq()
388 wake_up(&hda->waitq); in hda_dsp_check_ipc_irq()
413 if (!sps || !sdev->stream_box.size) { in hda_ipc_msg_data()
414 sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz); in hda_ipc_msg_data()
416 struct snd_pcm_substream *substream = sps->substream; in hda_ipc_msg_data()
417 struct hdac_stream *hstream = substream->runtime->private_data; in hda_ipc_msg_data()
426 return -ESTRPIPE; in hda_ipc_msg_data()
428 sof_mailbox_read(sdev, hda_stream->sof_intel_stream.posn_offset, p, sz); in hda_ipc_msg_data()
439 struct snd_pcm_substream *substream = sps->substream; in hda_set_stream_data_offset()
440 struct hdac_stream *hstream = substream->runtime->private_data; in hda_set_stream_data_offset()
447 if (posn_offset > sdev->stream_box.size || in hda_set_stream_data_offset()
449 return -EINVAL; in hda_set_stream_data_offset()
451 hda_stream->sof_intel_stream.posn_offset = sdev->stream_box.offset + posn_offset; in hda_set_stream_data_offset()
453 dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu", in hda_set_stream_data_offset()
454 substream->stream, hda_stream->sof_intel_stream.posn_offset); in hda_set_stream_data_offset()
478 chip = get_chip_info(sdev->pdata); in hda_check_ipc_irq()
479 if (chip && chip->check_ipc_irq) in hda_check_ipc_irq()
480 return chip->check_ipc_irq(sdev); in hda_check_ipc_irq()
494 /* read key IRQ stats and config registers */ in hda_ipc_irq_dump()
501 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", in hda_ipc_irq_dump()
503 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); in hda_ipc_irq_dump()
522 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", in hda_ipc_dump()
541 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", in hda_ipc4_dump()
548 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_ipc4_tx_is_busy()
549 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_ipc4_tx_is_busy()
552 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); in hda_ipc4_tx_is_busy()
554 return !!(val & chip->ipc_req_mask); in hda_ipc4_tx_is_busy()