1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
15  * Hardware interface for generic Intel audio DSP HDA IP
22 #include <sound/hda-mlink.h>
30 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)  in hda_dsp_ctrl_link_reset()  argument
36 	/* 0 to enter reset and 1 to exit reset */  in hda_dsp_ctrl_link_reset()
37 	val = reset ? 0 : SOF_HDA_GCTL_RESET;  in hda_dsp_ctrl_link_reset()
39 	/* enter/exit HDA controller reset */  in hda_dsp_ctrl_link_reset()
43 	/* wait to enter/exit reset */  in hda_dsp_ctrl_link_reset()
52 	/* enter/exit reset failed */  in hda_dsp_ctrl_link_reset()
53 	dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",  in hda_dsp_ctrl_link_reset()
54 		reset ? "reset" : "ready", gctl);  in hda_dsp_ctrl_link_reset()
55 	return -EIO;  in hda_dsp_ctrl_link_reset()
66 	 * On some devices, one reset cycle is necessary before reading  in hda_dsp_ctrl_get_caps()
79 		dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",  in hda_dsp_ctrl_get_caps()
84 		if (cap == -1) {  in hda_dsp_ctrl_get_caps()
85 			dev_dbg(bus->dev, "Invalid capability reg read\n");  in hda_dsp_ctrl_get_caps()
93 			dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
95 			bus->ppcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
96 			sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;  in hda_dsp_ctrl_get_caps()
99 			dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
101 			bus->spbcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
102 			sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;  in hda_dsp_ctrl_get_caps()
105 			dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
107 			bus->drsmcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
108 			sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;  in hda_dsp_ctrl_get_caps()
111 			dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
113 			bus->gtscap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
116 			dev_dbg(sdev->dev, "found ML capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
118 			bus->mlcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
121 			dev_dbg(sdev->dev, "found capability %d at 0x%x\n",  in hda_dsp_ctrl_get_caps()
159  * enable/disable audio dsp clock gating and power gating bits.
161  * the audio dsp when it is idle
165 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;  in hda_dsp_ctrl_clock_power_gating()
168 	/* enable/disable audio dsp clock gating */  in hda_dsp_ctrl_clock_power_gating()
174 	if (!enable || !hda->l1_disabled)  in hda_dsp_ctrl_clock_power_gating()
178 	/* enable/disable audio dsp power gating */  in hda_dsp_ctrl_clock_power_gating()
193 	if (bus->chip_init)  in hda_dsp_ctrl_init_chip()
200 	/* clear WAKE_STS if not in reset */  in hda_dsp_ctrl_init_chip()
206 	/* reset HDA controller */  in hda_dsp_ctrl_init_chip()
209 		dev_err(sdev->dev, "error: failed to reset HDA controller\n");  in hda_dsp_ctrl_init_chip()
215 	/* exit HDA controller reset */  in hda_dsp_ctrl_init_chip()
218 		dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");  in hda_dsp_ctrl_init_chip()
226 	list_for_each_entry(stream, &bus->stream_list, list) {  in hda_dsp_ctrl_init_chip()
235 			  bus->codec_mask);  in hda_dsp_ctrl_init_chip()
251 	if (bus->use_posbuf && bus->posbuf.addr) {  in hda_dsp_ctrl_init_chip()
253 				  (u32)bus->posbuf.addr);  in hda_dsp_ctrl_init_chip()
255 				  upper_32_bits(bus->posbuf.addr));  in hda_dsp_ctrl_init_chip()
260 	bus->chip_init = true;  in hda_dsp_ctrl_init_chip()
277 	if (!bus->chip_init)  in hda_dsp_ctrl_stop_chip()
281 	list_for_each_entry(stream, &bus->stream_list, list) {  in hda_dsp_ctrl_stop_chip()
300 	list_for_each_entry(stream, &bus->stream_list, list) {  in hda_dsp_ctrl_stop_chip()
320 	if (bus->use_posbuf && bus->posbuf.addr) {  in hda_dsp_ctrl_stop_chip()
327 	bus->chip_init = false;  in hda_dsp_ctrl_stop_chip()