Lines Matching +full:0 +full:x10e
8 #define MSM_AFE_PORT_TYPE_RX 0
15 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
18 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
25 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
27 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
29 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
31 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
33 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
35 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
37 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
39 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
41 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
43 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
45 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
48 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
50 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
52 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
54 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
56 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
58 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
60 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
62 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
64 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
66 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
68 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
71 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
74 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
78 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
80 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
82 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
84 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
86 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
88 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
90 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
92 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
94 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
97 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
101 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
103 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
105 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
107 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
109 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
111 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
113 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
115 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
117 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
120 #define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
122 #define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
124 #define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
126 #define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
128 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
130 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
132 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
134 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309
135 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a
136 #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
137 #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
138 #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
139 #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
140 #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b
141 #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310
143 #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2
144 #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3
145 #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4
148 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
150 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
152 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
154 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
156 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
158 #define Q6AFE_CMAP_INVALID 0xFFFF