Lines Matching +full:audio +full:- +full:asrc
1 // SPDX-License-Identifier: GPL-2.0
3 * mt2701-afe-clock-ctrl.c -- Mediatek 2701 afe clock ctrl
10 #include "mt2701-afe-common.h"
11 #include "mt2701-afe-clock-ctrl.h"
27 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_init_clock()
31 afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]); in mt2701_init_clock()
32 if (IS_ERR(afe_priv->base_ck[i])) { in mt2701_init_clock()
33 dev_err(afe->dev, "failed to get %s\n", base_clks[i]); in mt2701_init_clock()
34 return PTR_ERR(afe_priv->base_ck[i]); in mt2701_init_clock()
39 for (i = 0; i < afe_priv->soc->i2s_num; i++) { in mt2701_init_clock()
40 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i]; in mt2701_init_clock()
45 i2s_path->sel_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
46 if (IS_ERR(i2s_path->sel_ck)) { in mt2701_init_clock()
47 dev_err(afe->dev, "failed to get %s\n", name); in mt2701_init_clock()
48 return PTR_ERR(i2s_path->sel_ck); in mt2701_init_clock()
52 i2s_path->div_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
53 if (IS_ERR(i2s_path->div_ck)) { in mt2701_init_clock()
54 dev_err(afe->dev, "failed to get %s\n", name); in mt2701_init_clock()
55 return PTR_ERR(i2s_path->div_ck); in mt2701_init_clock()
59 i2s_path->mclk_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
60 if (IS_ERR(i2s_path->mclk_ck)) { in mt2701_init_clock()
61 dev_err(afe->dev, "failed to get %s\n", name); in mt2701_init_clock()
62 return PTR_ERR(i2s_path->mclk_ck); in mt2701_init_clock()
66 i2s_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
68 dev_err(afe->dev, "failed to get %s\n", name); in mt2701_init_clock()
71 i2s_path->hop_ck[SNDRV_PCM_STREAM_PLAYBACK] = i2s_ck; in mt2701_init_clock()
74 i2s_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
76 dev_err(afe->dev, "failed to get %s\n", name); in mt2701_init_clock()
79 i2s_path->hop_ck[SNDRV_PCM_STREAM_CAPTURE] = i2s_ck; in mt2701_init_clock()
81 snprintf(name, sizeof(name), "asrc%d_out_ck", i); in mt2701_init_clock()
82 i2s_path->asrco_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
83 if (IS_ERR(i2s_path->asrco_ck)) { in mt2701_init_clock()
84 dev_err(afe->dev, "failed to get %s\n", name); in mt2701_init_clock()
85 return PTR_ERR(i2s_path->asrco_ck); in mt2701_init_clock()
90 afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd"); in mt2701_init_clock()
91 if (IS_ERR(afe_priv->mrgif_ck)) { in mt2701_init_clock()
92 if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER) in mt2701_init_clock()
93 return -EPROBE_DEFER; in mt2701_init_clock()
95 afe_priv->mrgif_ck = NULL; in mt2701_init_clock()
107 ret = clk_prepare_enable(i2s_path->asrco_ck); in mt2701_afe_enable_i2s()
109 dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret); in mt2701_afe_enable_i2s()
113 ret = clk_prepare_enable(i2s_path->hop_ck[dir]); in mt2701_afe_enable_i2s()
115 dev_err(afe->dev, "failed to enable I2S clock %d\n", ret); in mt2701_afe_enable_i2s()
122 clk_disable_unprepare(i2s_path->asrco_ck); in mt2701_afe_enable_i2s()
131 clk_disable_unprepare(i2s_path->hop_ck[dir]); in mt2701_afe_disable_i2s()
132 clk_disable_unprepare(i2s_path->asrco_ck); in mt2701_afe_disable_i2s()
137 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_afe_enable_mclk()
138 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; in mt2701_afe_enable_mclk()
140 return clk_prepare_enable(i2s_path->mclk_ck); in mt2701_afe_enable_mclk()
145 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_afe_disable_mclk()
146 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; in mt2701_afe_disable_mclk()
148 clk_disable_unprepare(i2s_path->mclk_ck); in mt2701_afe_disable_mclk()
153 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_enable_btmrg_clk()
155 return clk_prepare_enable(afe_priv->mrgif_ck); in mt2701_enable_btmrg_clk()
160 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_disable_btmrg_clk()
162 clk_disable_unprepare(afe_priv->mrgif_ck); in mt2701_disable_btmrg_clk()
167 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_afe_enable_audsys()
171 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]); in mt2701_afe_enable_audsys()
176 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]); in mt2701_afe_enable_audsys()
181 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]); in mt2701_afe_enable_audsys()
186 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]); in mt2701_afe_enable_audsys()
190 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); in mt2701_afe_enable_audsys()
194 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); in mt2701_afe_enable_audsys()
198 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]); in mt2701_afe_enable_audsys()
205 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); in mt2701_afe_enable_audsys()
207 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); in mt2701_afe_enable_audsys()
209 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]); in mt2701_afe_enable_audsys()
211 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]); in mt2701_afe_enable_audsys()
213 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]); in mt2701_afe_enable_audsys()
215 clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]); in mt2701_afe_enable_audsys()
222 struct mt2701_afe_private *afe_priv = afe->platform_priv; in mt2701_afe_disable_audsys()
224 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]); in mt2701_afe_disable_audsys()
225 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); in mt2701_afe_disable_audsys()
226 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); in mt2701_afe_disable_audsys()
227 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]); in mt2701_afe_disable_audsys()
228 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]); in mt2701_afe_disable_audsys()
229 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]); in mt2701_afe_disable_audsys()
230 clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]); in mt2701_afe_disable_audsys()
237 /* Enable audio system */ in mt2701_afe_enable_clock()
240 dev_err(afe->dev, "failed to enable audio system %d\n", ret); in mt2701_afe_enable_clock()
244 regmap_update_bits(afe->regmap, ASYS_TOP_CON, in mt2701_afe_enable_clock()
247 regmap_update_bits(afe->regmap, AFE_DAC_CON0, in mt2701_afe_enable_clock()
251 /* Configure ASRC */ in mt2701_afe_enable_clock()
252 regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL); in mt2701_afe_enable_clock()
253 regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL); in mt2701_afe_enable_clock()
260 regmap_update_bits(afe->regmap, ASYS_TOP_CON, in mt2701_afe_disable_clock()
262 regmap_update_bits(afe->regmap, AFE_DAC_CON0, in mt2701_afe_disable_clock()
273 struct mt2701_afe_private *priv = afe->platform_priv; in mt2701_mclk_configuration()
274 struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id]; in mt2701_mclk_configuration()
275 int ret = -EINVAL; in mt2701_mclk_configuration()
278 if (!(MT2701_PLL_DOMAIN_0_RATE % i2s_path->mclk_rate)) in mt2701_mclk_configuration()
279 ret = clk_set_parent(i2s_path->sel_ck, in mt2701_mclk_configuration()
280 priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]); in mt2701_mclk_configuration()
281 else if (!(MT2701_PLL_DOMAIN_1_RATE % i2s_path->mclk_rate)) in mt2701_mclk_configuration()
282 ret = clk_set_parent(i2s_path->sel_ck, in mt2701_mclk_configuration()
283 priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]); in mt2701_mclk_configuration()
286 dev_err(afe->dev, "failed to set mclk source\n"); in mt2701_mclk_configuration()
291 ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate); in mt2701_mclk_configuration()
293 dev_err(afe->dev, "failed to set mclk divider %d\n", ret); in mt2701_mclk_configuration()