80 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)  in hi6210_write_reg()  argument
82 	writel(val, i2s->base + reg);  in hi6210_write_reg()
95 	u32 val;  in hi6210_i2s_startup()  local
98 	regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);  in hi6210_i2s_startup()
99 	if (val & BIT(4))  in hi6210_i2s_startup()
126 	val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);  in hi6210_i2s_startup()
127 	val |= 0x3f;  in hi6210_i2s_startup()
128 	hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);  in hi6210_i2s_startup()
132 	val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);  in hi6210_i2s_startup()
133 	val |= (BIT(5) | BIT(4));  in hi6210_i2s_startup()
134 	hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);  in hi6210_i2s_startup()
136 	val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);  in hi6210_i2s_startup()
137 	val &= ~(BIT(5) | BIT(4));  in hi6210_i2s_startup()
138 	hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);  in hi6210_i2s_startup()
141 	val = hi6210_read_reg(i2s, HII2S_SW_RST_N);  in hi6210_i2s_startup()
142 	val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<  in hi6210_i2s_startup()
144 	val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);  in hi6210_i2s_startup()
145 	hi6210_write_reg(i2s, HII2S_SW_RST_N, val);  in hi6210_i2s_startup()
147 	val = hi6210_read_reg(i2s, HII2S_MISC_CFG);  in hi6210_i2s_startup()
149 	val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;  in hi6210_i2s_startup()
151 	val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;  in hi6210_i2s_startup()
152 	val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;  in hi6210_i2s_startup()
154 	val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;  in hi6210_i2s_startup()
156 	val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;  in hi6210_i2s_startup()
157 	hi6210_write_reg(i2s, HII2S_MISC_CFG, val);  in hi6210_i2s_startup()
159 	val = hi6210_read_reg(i2s, HII2S_SW_RST_N);  in hi6210_i2s_startup()
160 	val |= HII2S_SW_RST_N__SW_RST_N;  in hi6210_i2s_startup()
161 	hi6210_write_reg(i2s, HII2S_SW_RST_N, val);  in hi6210_i2s_startup()
186 	u32 val;  in hi6210_i2s_txctrl()  local
191 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_txctrl()
192 		val |= HII2S_I2S_CFG__S2_IF_TX_EN;  in hi6210_i2s_txctrl()
193 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_txctrl()
196 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_txctrl()
197 		val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;  in hi6210_i2s_txctrl()
198 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_txctrl()
206 	u32 val;  in hi6210_i2s_rxctrl()  local
210 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_rxctrl()
211 		val |= HII2S_I2S_CFG__S2_IF_RX_EN;  in hi6210_i2s_rxctrl()
212 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_rxctrl()
214 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_rxctrl()
215 		val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;  in hi6210_i2s_rxctrl()
216 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_rxctrl()
259 	u32 val;  in hi6210_i2s_hw_params()  local
326 	val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);  in hi6210_i2s_hw_params()
327 	val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<  in hi6210_i2s_hw_params()
335 	val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |  in hi6210_i2s_hw_params()
339 	hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);  in hi6210_i2s_hw_params()
342 	val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);  in hi6210_i2s_hw_params()
343 	val |= (BIT(19) | BIT(18) | BIT(17) |  in hi6210_i2s_hw_params()
349 	hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);  in hi6210_i2s_hw_params()
352 	val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);  in hi6210_i2s_hw_params()
353 	val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |  in hi6210_i2s_hw_params()
359 	val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |  in hi6210_i2s_hw_params()
361 	hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);  in hi6210_i2s_hw_params()
364 	val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);  in hi6210_i2s_hw_params()
365 	val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |  in hi6210_i2s_hw_params()
367 	hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);  in hi6210_i2s_hw_params()
369 	val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);  in hi6210_i2s_hw_params()
370 	val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |  in hi6210_i2s_hw_params()
374 	hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);  in hi6210_i2s_hw_params()
380 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
381 		val |= HII2S_I2S_CFG__S2_MST_SLV;  in hi6210_i2s_hw_params()
382 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
386 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
387 		val &= ~HII2S_I2S_CFG__S2_MST_SLV;  in hi6210_i2s_hw_params()
388 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
410 	val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
411 	val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<  in hi6210_i2s_hw_params()
413 	val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;  in hi6210_i2s_hw_params()
414 	hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
417 	val = hi6210_read_reg(i2s, HII2S_CLK_SEL);  in hi6210_i2s_hw_params()
418 	val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */  in hi6210_i2s_hw_params()
420 	hi6210_write_reg(i2s, HII2S_CLK_SEL, val);  in hi6210_i2s_hw_params()
431 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
432 		val |= HII2S_I2S_CFG__S2_FRAME_MODE;  in hi6210_i2s_hw_params()
433 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
436 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
437 		val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;  in hi6210_i2s_hw_params()
438 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
443 	val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
444 	val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;  in hi6210_i2s_hw_params()
445 	val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<  in hi6210_i2s_hw_params()
447 	val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<  in hi6210_i2s_hw_params()
449 	val |= signed_data;  in hi6210_i2s_hw_params()
450 	val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);  in hi6210_i2s_hw_params()
451 	hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
458 	val = hi6210_read_reg(i2s, HII2S_FS_CFG);  in hi6210_i2s_hw_params()
459 	val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);  in hi6210_i2s_hw_params()
460 	val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);  in hi6210_i2s_hw_params()
461 	val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<  in hi6210_i2s_hw_params()
463 	val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<  in hi6210_i2s_hw_params()
465 	val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);  in hi6210_i2s_hw_params()
466 	val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);  in hi6210_i2s_hw_params()
467 	val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);  in hi6210_i2s_hw_params()
468 	val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);  in hi6210_i2s_hw_params()
469 	hi6210_write_reg(i2s, HII2S_FS_CFG, val);  in hi6210_i2s_hw_params()