3  * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
31 #include "hi6210-i2s.h"
80 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)  in hi6210_write_reg()  argument
82 	writel(val, i2s->base + reg);  in hi6210_write_reg()
85 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)  in hi6210_read_reg()  argument
87 	return readl(i2s->base + reg);  in hi6210_read_reg()
93 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_startup()  local
98 	regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);  in hi6210_i2s_startup()
100 		regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));  in hi6210_i2s_startup()
102 	for (n = 0; n < i2s->clocks; n++) {  in hi6210_i2s_startup()
103 		ret = clk_prepare_enable(i2s->clk[n]);  in hi6210_i2s_startup()
108 	ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);  in hi6210_i2s_startup()
110 		dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",  in hi6210_i2s_startup()
116 	regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));  in hi6210_i2s_startup()
119 	regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));  in hi6210_i2s_startup()
122 	regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));  in hi6210_i2s_startup()
123 	regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));  in hi6210_i2s_startup()
125 	/* not interested in i2s irqs */  in hi6210_i2s_startup()
126 	val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);  in hi6210_i2s_startup()
128 	hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);  in hi6210_i2s_startup()
132 	val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);  in hi6210_i2s_startup()
134 	hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);  in hi6210_i2s_startup()
136 	val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);  in hi6210_i2s_startup()
138 	hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);  in hi6210_i2s_startup()
141 	val = hi6210_read_reg(i2s, HII2S_SW_RST_N);  in hi6210_i2s_startup()
145 	hi6210_write_reg(i2s, HII2S_SW_RST_N, val);  in hi6210_i2s_startup()
147 	val = hi6210_read_reg(i2s, HII2S_MISC_CFG);  in hi6210_i2s_startup()
148 	/* mux 11/12 = APB not i2s */  in hi6210_i2s_startup()
157 	hi6210_write_reg(i2s, HII2S_MISC_CFG, val);  in hi6210_i2s_startup()
159 	val = hi6210_read_reg(i2s, HII2S_SW_RST_N);  in hi6210_i2s_startup()
161 	hi6210_write_reg(i2s, HII2S_SW_RST_N, val);  in hi6210_i2s_startup()
167 		clk_disable_unprepare(i2s->clk[n]);  in hi6210_i2s_startup()
174 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_shutdown()  local
177 	for (n = 0; n < i2s->clocks; n++)  in hi6210_i2s_shutdown()
178 		clk_disable_unprepare(i2s->clk[n]);  in hi6210_i2s_shutdown()
180 	regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));  in hi6210_i2s_shutdown()
185 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_txctrl()  local
188 	spin_lock(&i2s->lock);  in hi6210_i2s_txctrl()
191 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_txctrl()
193 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_txctrl()
196 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_txctrl()
198 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_txctrl()
200 	spin_unlock(&i2s->lock);  in hi6210_i2s_txctrl()
205 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_rxctrl()  local
208 	spin_lock(&i2s->lock);  in hi6210_i2s_rxctrl()
210 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_rxctrl()
212 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_rxctrl()
214 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_rxctrl()
216 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_rxctrl()
218 	spin_unlock(&i2s->lock);  in hi6210_i2s_rxctrl()
223 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_set_fmt()  local
246 	i2s->format = fmt;  in hi6210_i2s_set_fmt()
247 	i2s->master = (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==  in hi6210_i2s_set_fmt()
257 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_hw_params()  local
314 		i2s->bits = 32;  in hi6210_i2s_hw_params()
318 		i2s->bits = 16;  in hi6210_i2s_hw_params()
322 	i2s->rate = params_rate(params);  in hi6210_i2s_hw_params()
323 	i2s->channels = params_channels(params);  in hi6210_i2s_hw_params()
324 	i2s->channel_length = i2s->channels * i2s->bits;  in hi6210_i2s_hw_params()
326 	val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);  in hi6210_i2s_hw_params()
339 	hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);  in hi6210_i2s_hw_params()
342 	val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);  in hi6210_i2s_hw_params()
349 	hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);  in hi6210_i2s_hw_params()
352 	val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);  in hi6210_i2s_hw_params()
361 	hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);  in hi6210_i2s_hw_params()
364 	val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);  in hi6210_i2s_hw_params()
367 	hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);  in hi6210_i2s_hw_params()
369 	val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);  in hi6210_i2s_hw_params()
374 	hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);  in hi6210_i2s_hw_params()
377 	switch (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {  in hi6210_i2s_hw_params()
379 		i2s->master = false;  in hi6210_i2s_hw_params()
380 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
382 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
385 		i2s->master = true;  in hi6210_i2s_hw_params()
386 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
388 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
391 		WARN_ONCE(1, "Invalid i2s->fmt CLOCK_PROVIDER_MASK. This shouldn't happen\n");  in hi6210_i2s_hw_params()
395 	switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {  in hi6210_i2s_hw_params()
406 		WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");  in hi6210_i2s_hw_params()
410 	val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
414 	hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
417 	val = hi6210_read_reg(i2s, HII2S_CLK_SEL);  in hi6210_i2s_hw_params()
418 	val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */  in hi6210_i2s_hw_params()
420 	hi6210_write_reg(i2s, HII2S_CLK_SEL, val);  in hi6210_i2s_hw_params()
425 		dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;  in hi6210_i2s_hw_params()
427 		dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;  in hi6210_i2s_hw_params()
429 	switch (i2s->channels) {  in hi6210_i2s_hw_params()
431 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
433 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
436 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
438 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
443 	val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
451 	hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
454 	if (!i2s->master)  in hi6210_i2s_hw_params()
458 	val = hi6210_read_reg(i2s, HII2S_FS_CFG);  in hi6210_i2s_hw_params()
469 	hi6210_write_reg(i2s, HII2S_FS_CFG, val);  in hi6210_i2s_hw_params()
502 	struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);  in hi6210_i2s_dai_probe()  local
505 				  &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],  in hi6210_i2s_dai_probe()
506 				  &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);  in hi6210_i2s_dai_probe()
540 	.name = "hi6210_i2s-i2s",
548 	struct hi6210_i2s *i2s;  in hi6210_i2s_probe()  local
552 	i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);  in hi6210_i2s_probe()
553 	if (!i2s)  in hi6210_i2s_probe()
556 	i2s->dev = dev;  in hi6210_i2s_probe()
557 	spin_lock_init(&i2s->lock);  in hi6210_i2s_probe()
559 	i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in hi6210_i2s_probe()
560 	if (IS_ERR(i2s->base))  in hi6210_i2s_probe()
561 		return PTR_ERR(i2s->base);  in hi6210_i2s_probe()
563 	i2s->base_phys = (phys_addr_t)res->start;  in hi6210_i2s_probe()
564 	i2s->dai = hi6210_i2s_dai_init;  in hi6210_i2s_probe()
566 	dev_set_drvdata(dev, i2s);  in hi6210_i2s_probe()
568 	i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,  in hi6210_i2s_probe()
570 	if (IS_ERR(i2s->sysctrl))  in hi6210_i2s_probe()
571 		return PTR_ERR(i2s->sysctrl);  in hi6210_i2s_probe()
573 	i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec");  in hi6210_i2s_probe()
574 	if (IS_ERR(i2s->clk[CLK_DACODEC]))  in hi6210_i2s_probe()
575 		return PTR_ERR(i2s->clk[CLK_DACODEC]);  in hi6210_i2s_probe()
576 	i2s->clocks++;  in hi6210_i2s_probe()
578 	i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base");  in hi6210_i2s_probe()
579 	if (IS_ERR(i2s->clk[CLK_I2S_BASE]))  in hi6210_i2s_probe()
580 		return PTR_ERR(i2s->clk[CLK_I2S_BASE]);  in hi6210_i2s_probe()
581 	i2s->clocks++;  in hi6210_i2s_probe()
588 					 &i2s->dai, 1);  in hi6210_i2s_probe()
593 	{ .compatible = "hisilicon,hi6210-i2s" },
609 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");