Lines Matching +full:half +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 	struct mutex lock; /* To serialize user-space access */
43 #define LPC3XXX_I2S_WW8      FIELD_PREP(0x3, 0) /* Word width is 8bit */
44 #define LPC3XXX_I2S_WW16     FIELD_PREP(0x3, 1) /* Word width is 16bit */
45 #define LPC3XXX_I2S_WW32     FIELD_PREP(0x3, 3) /* Word width is 32bit */
46 #define LPC3XXX_I2S_MONO     BIT(2)   /* Mono */
47 #define LPC3XXX_I2S_STOP     BIT(3)   /* Stop, diables the access to FIFO, mutes the channel */
48 #define LPC3XXX_I2S_RESET    BIT(4)   /* Reset the channel */
49 #define LPC3XXX_I2S_WS_SEL   BIT(5)   /* Channel Master(0) or slave(1) mode select */
50 #define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
51 #define LPC3XXX_I2S_MUTE     BIT(15)  /* Mute the channel, Transmit channel only */
53 #define LPC3XXX_I2S_WW32_HP  0x1f /* Word select half period for 32bit word width */
54 #define LPC3XXX_I2S_WW16_HP  0x0f /* Word select half period for 16bit word width */
55 #define LPC3XXX_I2S_WW8_HP   0x7  /* Word select half period for 8bit word width */
58 #define LPC3XXX_I2S_IRQ_STAT     BIT(0)
59 #define LPC3XXX_I2S_DMA0_REQ     BIT(1)
60 #define LPC3XXX_I2S_DMA1_REQ     BIT(2)
63 #define LPC3XXX_I2S_DMA0_RX_EN     BIT(0)       /* Enable RX DMA1 */
64 #define LPC3XXX_I2S_DMA0_TX_EN     BIT(1)       /* Enable TX DMA1 */
69 #define LPC3XXX_I2S_DMA1_RX_EN     BIT(0)       /* Enable RX DMA1 */
70 #define LPC3XXX_I2S_DMA1_TX_EN     BIT(1)       /* Enable TX DMA1 */
75 #define LPC3XXX_I2S_RX_IRQ_EN     BIT(0)       /* Enable RX IRQ */
76 #define LPC3XXX_I2S_TX_IRQ_EN     BIT(1)       /* Enable TX IRQ */