Lines Matching +full:xcvr +full:- +full:setup
1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
115 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_arc_mode_put() local
116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
117 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
128 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_arc_mode_get() local
130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
151 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
160 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_capds_get() local
162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
171 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_capds_put() local
173 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_put()
190 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_activate_ctl()
194 lockdep_assert_held(&card->snd_card->controls_rwsem); in fsl_xcvr_activate_ctl()
198 return -ENOENT; in fsl_xcvr_activate_ctl()
200 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); in fsl_xcvr_activate_ctl()
205 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
207 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
209 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); in fsl_xcvr_activate_ctl()
218 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_mode_put() local
219 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_mode_put()
220 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_mode_put()
221 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_mode_put()
224 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_mode_put()
227 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_mode_put()
229 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_mode_put()
231 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); in fsl_xcvr_mode_put()
232 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = in fsl_xcvr_mode_put()
233 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); in fsl_xcvr_mode_put()
241 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_mode_get() local
243 ucontrol->value.enumerated.item[0] = xcvr->mode; in fsl_xcvr_mode_get()
252 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
256 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) in fsl_xcvr_ai_write() argument
258 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_ai_write()
265 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); in fsl_xcvr_ai_write()
266 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); in fsl_xcvr_ai_write()
267 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); in fsl_xcvr_ai_write()
268 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); in fsl_xcvr_ai_write()
270 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, in fsl_xcvr_ai_write()
279 static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) in fsl_xcvr_ai_read() argument
281 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_ai_read()
288 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); in fsl_xcvr_ai_read()
289 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); in fsl_xcvr_ai_read()
290 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); in fsl_xcvr_ai_read()
292 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, in fsl_xcvr_ai_read()
299 regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); in fsl_xcvr_ai_read()
306 struct fsl_xcvr *xcvr = context; in fsl_xcvr_phy_reg_read() local
308 return fsl_xcvr_ai_read(xcvr, reg, val, 1); in fsl_xcvr_phy_reg_read()
313 struct fsl_xcvr *xcvr = context; in fsl_xcvr_phy_reg_write() local
315 return fsl_xcvr_ai_write(xcvr, reg, val, 1); in fsl_xcvr_phy_reg_write()
320 struct fsl_xcvr *xcvr = context; in fsl_xcvr_pll_reg_read() local
322 return fsl_xcvr_ai_read(xcvr, reg, val, 0); in fsl_xcvr_pll_reg_read()
327 struct fsl_xcvr *xcvr = context; in fsl_xcvr_pll_reg_write() local
329 return fsl_xcvr_ai_write(xcvr, reg, val, 0); in fsl_xcvr_pll_reg_write()
332 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) in fsl_xcvr_en_phy_pll() argument
334 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_phy_pll()
338 if (!xcvr->soc_data->use_phy) in fsl_xcvr_en_phy_pll()
349 return -EINVAL; in fsl_xcvr_en_phy_pll()
354 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_phy_pll()
361 switch (xcvr->soc_data->pll_ver) { in fsl_xcvr_en_phy_pll()
364 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, in fsl_xcvr_en_phy_pll()
368 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); in fsl_xcvr_en_phy_pll()
370 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); in fsl_xcvr_en_phy_pll()
372 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); in fsl_xcvr_en_phy_pll()
374 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, in fsl_xcvr_en_phy_pll()
378 regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, in fsl_xcvr_en_phy_pll()
383 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
386 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, in fsl_xcvr_en_phy_pll()
388 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ in fsl_xcvr_en_phy_pll()
390 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
393 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, in fsl_xcvr_en_phy_pll()
397 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
400 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, in fsl_xcvr_en_phy_pll()
406 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); in fsl_xcvr_en_phy_pll()
408 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); in fsl_xcvr_en_phy_pll()
409 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, in fsl_xcvr_en_phy_pll()
412 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); in fsl_xcvr_en_phy_pll()
415 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); in fsl_xcvr_en_phy_pll()
416 return -EINVAL; in fsl_xcvr_en_phy_pll()
419 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_phy_pll()
421 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, in fsl_xcvr_en_phy_pll()
425 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, in fsl_xcvr_en_phy_pll()
428 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_en_phy_pll()
430 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, in fsl_xcvr_en_phy_pll()
432 else /* PHY: CTRL_SET: ARC RX setup */ in fsl_xcvr_en_phy_pll()
433 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, in fsl_xcvr_en_phy_pll()
436 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); in fsl_xcvr_en_phy_pll()
445 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) in fsl_xcvr_en_aud_pll() argument
447 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_aud_pll()
450 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; in fsl_xcvr_en_aud_pll()
451 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
452 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, in fsl_xcvr_en_aud_pll()
453 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); in fsl_xcvr_en_aud_pll()
454 ret = clk_set_rate(xcvr->phy_clk, freq); in fsl_xcvr_en_aud_pll()
459 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
465 if (!xcvr->soc_data->use_phy) in fsl_xcvr_en_aud_pll()
468 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_aud_pll()
475 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_aud_pll()
477 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, in fsl_xcvr_en_aud_pll()
481 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, in fsl_xcvr_en_aud_pll()
485 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, in fsl_xcvr_en_aud_pll()
499 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_prepare() local
500 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_prepare()
502 u32 r = substream->runtime->rate, ch = substream->runtime->channels; in fsl_xcvr_prepare()
506 switch (xcvr->mode) { in fsl_xcvr_prepare()
508 if (xcvr->soc_data->spdif_only && tx) { in fsl_xcvr_prepare()
509 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, in fsl_xcvr_prepare()
513 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); in fsl_xcvr_prepare()
520 ret = fsl_xcvr_en_aud_pll(xcvr, fout); in fsl_xcvr_prepare()
522 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", in fsl_xcvr_prepare()
527 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, in fsl_xcvr_prepare()
530 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
535 * set SPDIF MODE - this flag is used to gate in fsl_xcvr_prepare()
545 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, in fsl_xcvr_prepare()
551 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
555 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); in fsl_xcvr_prepare()
557 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", in fsl_xcvr_prepare()
566 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, in fsl_xcvr_prepare()
570 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
575 ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, in fsl_xcvr_prepare()
579 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
592 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); in fsl_xcvr_prepare()
594 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); in fsl_xcvr_prepare()
605 struct snd_pcm_runtime *rt = substream->runtime; in fsl_xcvr_constr()
624 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_startup() local
625 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_startup()
628 if (xcvr->streams & BIT(substream->stream)) { in fsl_xcvr_startup()
629 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); in fsl_xcvr_startup()
630 return -EBUSY; in fsl_xcvr_startup()
637 if (xcvr->soc_data->use_edma) in fsl_xcvr_startup()
638 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_xcvr_startup()
640 tx ? xcvr->dma_prms_tx.maxburst : in fsl_xcvr_startup()
641 xcvr->dma_prms_rx.maxburst); in fsl_xcvr_startup()
643 switch (xcvr->mode) { in fsl_xcvr_startup()
646 if (xcvr->soc_data->spdif_only && tx) in fsl_xcvr_startup()
648 &xcvr->spdif_constr_rates); in fsl_xcvr_startup()
661 xcvr->streams |= BIT(substream->stream); in fsl_xcvr_startup()
663 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_startup()
664 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_startup()
666 /* Disable XCVR controls if there is stream started */ in fsl_xcvr_startup()
667 down_read(&card->snd_card->controls_rwsem); in fsl_xcvr_startup()
671 up_read(&card->snd_card->controls_rwsem); in fsl_xcvr_startup()
680 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_shutdown() local
681 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_shutdown()
685 xcvr->streams &= ~BIT(substream->stream); in fsl_xcvr_shutdown()
687 /* Enable XCVR controls if there is no stream started */ in fsl_xcvr_shutdown()
688 if (!xcvr->streams) { in fsl_xcvr_shutdown()
689 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_shutdown()
690 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_shutdown()
692 down_read(&card->snd_card->controls_rwsem); in fsl_xcvr_shutdown()
695 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_shutdown()
697 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_shutdown()
698 up_read(&card->snd_card->controls_rwsem); in fsl_xcvr_shutdown()
700 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_shutdown()
703 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); in fsl_xcvr_shutdown()
708 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_shutdown()
712 if (xcvr->mode == FSL_XCVR_MODE_EARC) { in fsl_xcvr_shutdown()
718 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_shutdown()
720 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); in fsl_xcvr_shutdown()
728 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_trigger() local
729 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_trigger()
733 spin_lock_irqsave(&xcvr->lock, lock_flags); in fsl_xcvr_trigger()
740 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
744 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret); in fsl_xcvr_trigger()
749 switch (xcvr->mode) { in fsl_xcvr_trigger()
752 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
756 dev_err(dai->dev, "err updating isr %d\n", ret); in fsl_xcvr_trigger()
761 ret = regmap_set_bits(xcvr->regmap, in fsl_xcvr_trigger()
765 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
773 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
776 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); in fsl_xcvr_trigger()
780 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_trigger()
783 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); in fsl_xcvr_trigger()
788 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
792 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); in fsl_xcvr_trigger()
801 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
805 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); in fsl_xcvr_trigger()
809 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_trigger()
812 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret); in fsl_xcvr_trigger()
817 switch (xcvr->mode) { in fsl_xcvr_trigger()
819 ret = regmap_clear_bits(xcvr->regmap, in fsl_xcvr_trigger()
823 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
826 if (xcvr->soc_data->spdif_only) in fsl_xcvr_trigger()
832 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
836 dev_err(dai->dev, in fsl_xcvr_trigger()
845 ret = -EINVAL; in fsl_xcvr_trigger()
850 spin_unlock_irqrestore(&xcvr->lock, lock_flags); in fsl_xcvr_trigger()
854 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) in fsl_xcvr_load_firmware() argument
856 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_load_firmware()
861 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); in fsl_xcvr_load_firmware()
867 rem = fw->size; in fsl_xcvr_load_firmware()
873 return -ENOMEM; in fsl_xcvr_load_firmware()
877 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_load_firmware()
891 memcpy_toio(xcvr->ram_addr, fw->data + off, out); in fsl_xcvr_load_firmware()
892 rem -= out; in fsl_xcvr_load_firmware()
896 memset_io(xcvr->ram_addr + out, 0, size - out); in fsl_xcvr_load_firmware()
900 memset_io(xcvr->ram_addr, 0, size); in fsl_xcvr_load_firmware()
920 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_load_firmware()
927 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, in fsl_xcvr_load_firmware()
935 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_xcvr_type_iec958_info()
936 uinfo->count = 1; in fsl_xcvr_type_iec958_info()
944 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_iec958_bytes_info()
945 uinfo->count = sizeof_field(struct snd_aes_iec958, status); in fsl_xcvr_type_iec958_bytes_info()
954 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_rx_cs_get() local
956 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); in fsl_xcvr_rx_cs_get()
965 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_tx_cs_get() local
967 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); in fsl_xcvr_tx_cs_get()
976 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_tx_cs_put() local
978 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); in fsl_xcvr_tx_cs_put()
1025 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_dai_probe() local
1027 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); in fsl_xcvr_dai_probe()
1029 if (xcvr->soc_data->spdif_only) in fsl_xcvr_dai_probe()
1030 xcvr->mode = FSL_XCVR_MODE_SPDIF; in fsl_xcvr_dai_probe()
1054 .stream_name = "CPU-Playback",
1063 .stream_name = "CPU-Capture",
1074 .name = "fsl-xcvr-dai",
1130 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_readable_reg() local
1132 if (!xcvr->soc_data->use_phy) in fsl_xcvr_readable_reg()
1203 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_writeable_reg() local
1205 if (!xcvr->soc_data->use_phy) in fsl_xcvr_writeable_reg()
1359 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); in reset_rx_work() local
1360 struct device *dev = &xcvr->pdev->dev; in reset_rx_work()
1365 spin_lock_irqsave(&xcvr->lock, lock_flags); in reset_rx_work()
1366 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl); in reset_rx_work()
1369 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in reset_rx_work()
1372 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in reset_rx_work()
1375 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in reset_rx_work()
1378 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in reset_rx_work()
1382 spin_unlock_irqrestore(&xcvr->lock, lock_flags); in reset_rx_work()
1387 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; in irq0_isr() local
1388 struct device *dev = &xcvr->pdev->dev; in irq0_isr()
1389 struct regmap *regmap = xcvr->regmap; in irq0_isr()
1398 if (!xcvr->soc_data->spdif_only) { in irq0_isr()
1400 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in irq0_isr()
1405 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; in irq0_isr()
1406 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; in irq0_isr()
1409 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; in irq0_isr()
1410 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; in irq0_isr()
1416 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, in irq0_isr()
1417 sizeof(xcvr->rx_iec958.status)); in irq0_isr()
1419 val = *(u32 *)(xcvr->rx_iec958.status + i*4); in irq0_isr()
1420 *(u32 *)(xcvr->rx_iec958.status + i*4) = in irq0_isr()
1477 schedule_work(&xcvr->work_rst); in irq0_isr()
1489 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1507 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1508 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1509 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data},
1516 struct device *dev = &pdev->dev; in fsl_xcvr_probe()
1517 struct fsl_xcvr *xcvr; in fsl_xcvr_probe() local
1522 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); in fsl_xcvr_probe()
1523 if (!xcvr) in fsl_xcvr_probe()
1524 return -ENOMEM; in fsl_xcvr_probe()
1526 xcvr->pdev = pdev; in fsl_xcvr_probe()
1527 xcvr->soc_data = of_device_get_match_data(&pdev->dev); in fsl_xcvr_probe()
1529 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); in fsl_xcvr_probe()
1530 if (IS_ERR(xcvr->ipg_clk)) { in fsl_xcvr_probe()
1532 return PTR_ERR(xcvr->ipg_clk); in fsl_xcvr_probe()
1535 xcvr->phy_clk = devm_clk_get(dev, "phy"); in fsl_xcvr_probe()
1536 if (IS_ERR(xcvr->phy_clk)) { in fsl_xcvr_probe()
1538 return PTR_ERR(xcvr->phy_clk); in fsl_xcvr_probe()
1541 xcvr->spba_clk = devm_clk_get(dev, "spba"); in fsl_xcvr_probe()
1542 if (IS_ERR(xcvr->spba_clk)) { in fsl_xcvr_probe()
1544 return PTR_ERR(xcvr->spba_clk); in fsl_xcvr_probe()
1547 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); in fsl_xcvr_probe()
1548 if (IS_ERR(xcvr->pll_ipg_clk)) { in fsl_xcvr_probe()
1550 return PTR_ERR(xcvr->pll_ipg_clk); in fsl_xcvr_probe()
1553 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, in fsl_xcvr_probe()
1554 &xcvr->pll11k_clk); in fsl_xcvr_probe()
1556 if (xcvr->soc_data->spdif_only) { in fsl_xcvr_probe()
1557 if (!(xcvr->pll8k_clk || xcvr->pll11k_clk)) in fsl_xcvr_probe()
1558 xcvr->pll8k_clk = xcvr->phy_clk; in fsl_xcvr_probe()
1559 fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates, in fsl_xcvr_probe()
1561 xcvr->pll8k_clk, xcvr->pll11k_clk, NULL, in fsl_xcvr_probe()
1562 xcvr->spdif_constr_rates_list); in fsl_xcvr_probe()
1565 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); in fsl_xcvr_probe()
1566 if (IS_ERR(xcvr->ram_addr)) in fsl_xcvr_probe()
1567 return PTR_ERR(xcvr->ram_addr); in fsl_xcvr_probe()
1573 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, in fsl_xcvr_probe()
1575 if (IS_ERR(xcvr->regmap)) { in fsl_xcvr_probe()
1576 dev_err(dev, "failed to init XCVR regmap: %ld\n", in fsl_xcvr_probe()
1577 PTR_ERR(xcvr->regmap)); in fsl_xcvr_probe()
1578 return PTR_ERR(xcvr->regmap); in fsl_xcvr_probe()
1581 if (xcvr->soc_data->use_phy) { in fsl_xcvr_probe()
1582 xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, in fsl_xcvr_probe()
1584 if (IS_ERR(xcvr->regmap_phy)) { in fsl_xcvr_probe()
1585 dev_err(dev, "failed to init XCVR PHY regmap: %ld\n", in fsl_xcvr_probe()
1586 PTR_ERR(xcvr->regmap_phy)); in fsl_xcvr_probe()
1587 return PTR_ERR(xcvr->regmap_phy); in fsl_xcvr_probe()
1590 switch (xcvr->soc_data->pll_ver) { in fsl_xcvr_probe()
1592 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, in fsl_xcvr_probe()
1594 if (IS_ERR(xcvr->regmap_pll)) { in fsl_xcvr_probe()
1595 dev_err(dev, "failed to init XCVR PLL regmap: %ld\n", in fsl_xcvr_probe()
1596 PTR_ERR(xcvr->regmap_pll)); in fsl_xcvr_probe()
1597 return PTR_ERR(xcvr->regmap_pll); in fsl_xcvr_probe()
1601 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, in fsl_xcvr_probe()
1603 if (IS_ERR(xcvr->regmap_pll)) { in fsl_xcvr_probe()
1604 dev_err(dev, "failed to init XCVR PLL regmap: %ld\n", in fsl_xcvr_probe()
1605 PTR_ERR(xcvr->regmap_pll)); in fsl_xcvr_probe()
1606 return PTR_ERR(xcvr->regmap_pll); in fsl_xcvr_probe()
1610 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); in fsl_xcvr_probe()
1611 return -EINVAL; in fsl_xcvr_probe()
1615 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); in fsl_xcvr_probe()
1616 if (IS_ERR(xcvr->reset)) { in fsl_xcvr_probe()
1617 dev_err(dev, "failed to get XCVR reset control\n"); in fsl_xcvr_probe()
1618 return PTR_ERR(xcvr->reset); in fsl_xcvr_probe()
1626 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); in fsl_xcvr_probe()
1636 return -EINVAL; in fsl_xcvr_probe()
1638 xcvr->dma_prms_rx.chan_name = "rx"; in fsl_xcvr_probe()
1639 xcvr->dma_prms_tx.chan_name = "tx"; in fsl_xcvr_probe()
1640 xcvr->dma_prms_rx.addr = rx_res->start; in fsl_xcvr_probe()
1641 xcvr->dma_prms_tx.addr = tx_res->start; in fsl_xcvr_probe()
1642 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; in fsl_xcvr_probe()
1643 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; in fsl_xcvr_probe()
1645 platform_set_drvdata(pdev, xcvr); in fsl_xcvr_probe()
1647 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_probe()
1648 if (xcvr->soc_data->use_phy) { in fsl_xcvr_probe()
1649 regcache_cache_only(xcvr->regmap_phy, true); in fsl_xcvr_probe()
1650 regcache_cache_only(xcvr->regmap_pll, true); in fsl_xcvr_probe()
1672 INIT_WORK(&xcvr->work_rst, reset_rx_work); in fsl_xcvr_probe()
1673 spin_lock_init(&xcvr->lock); in fsl_xcvr_probe()
1679 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev); in fsl_xcvr_remove() local
1681 cancel_work_sync(&xcvr->work_rst); in fsl_xcvr_remove()
1682 pm_runtime_disable(&pdev->dev); in fsl_xcvr_remove()
1687 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_runtime_suspend() local
1690 if (!xcvr->soc_data->spdif_only && in fsl_xcvr_runtime_suspend()
1691 xcvr->mode == FSL_XCVR_MODE_EARC) { in fsl_xcvr_runtime_suspend()
1693 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_suspend()
1700 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_runtime_suspend()
1701 if (xcvr->soc_data->use_phy) { in fsl_xcvr_runtime_suspend()
1702 regcache_cache_only(xcvr->regmap_phy, true); in fsl_xcvr_runtime_suspend()
1703 regcache_cache_only(xcvr->regmap_pll, true); in fsl_xcvr_runtime_suspend()
1706 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_suspend()
1707 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_suspend()
1708 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_suspend()
1709 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_suspend()
1716 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_runtime_resume() local
1719 ret = reset_control_assert(xcvr->reset); in fsl_xcvr_runtime_resume()
1725 ret = clk_prepare_enable(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1731 ret = clk_prepare_enable(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1737 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1743 ret = clk_prepare_enable(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1749 ret = reset_control_deassert(xcvr->reset); in fsl_xcvr_runtime_resume()
1755 regcache_cache_only(xcvr->regmap, false); in fsl_xcvr_runtime_resume()
1756 regcache_mark_dirty(xcvr->regmap); in fsl_xcvr_runtime_resume()
1757 ret = regcache_sync(xcvr->regmap); in fsl_xcvr_runtime_resume()
1764 if (xcvr->soc_data->use_phy) { in fsl_xcvr_runtime_resume()
1765 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_runtime_resume()
1772 regcache_cache_only(xcvr->regmap_phy, false); in fsl_xcvr_runtime_resume()
1773 regcache_mark_dirty(xcvr->regmap_phy); in fsl_xcvr_runtime_resume()
1774 ret = regcache_sync(xcvr->regmap_phy); in fsl_xcvr_runtime_resume()
1780 regcache_cache_only(xcvr->regmap_pll, false); in fsl_xcvr_runtime_resume()
1781 regcache_mark_dirty(xcvr->regmap_pll); in fsl_xcvr_runtime_resume()
1782 ret = regcache_sync(xcvr->regmap_pll); in fsl_xcvr_runtime_resume()
1789 if (xcvr->mode == FSL_XCVR_MODE_EARC) { in fsl_xcvr_runtime_resume()
1790 ret = fsl_xcvr_load_firmware(xcvr); in fsl_xcvr_runtime_resume()
1797 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_resume()
1811 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1813 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1815 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1817 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1831 .name = "fsl,imx8mp-audio-xcvr",
1840 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");