1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18  * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
42 		return -EINVAL;  in fsl_asoc_get_dma_channel()
44 	if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {  in fsl_asoc_get_dma_channel()
46 		return -EINVAL;  in fsl_asoc_get_dma_channel()
55 	 * dai->platform name should already point to an allocated buffer.  in fsl_asoc_get_dma_channel()
62 	snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn",  in fsl_asoc_get_dma_channel()
65 	iprop = of_get_property(dma_channel_np, "cell-index", NULL);  in fsl_asoc_get_dma_channel()
68 		return -EINVAL;  in fsl_asoc_get_dma_channel()
73 	iprop = of_get_property(dma_np, "cell-index", NULL);  in fsl_asoc_get_dma_channel()
77 		return -EINVAL;  in fsl_asoc_get_dma_channel()
89  * fsl_asoc_get_pll_clocks - get two PLL clock source
95  * This function get two PLL clock source
97 void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,  in fsl_asoc_get_pll_clocks()
98 			     struct clk **pll11k_clk)  in fsl_asoc_get_pll_clocks()
111  * fsl_asoc_reparent_pll_clocks - set clock parent if necessary
114  * @clk: root clock pointer
121 void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,  in fsl_asoc_reparent_pll_clocks()  argument
122 				  struct clk *pll8k_clk,  in fsl_asoc_reparent_pll_clocks()
123 				  struct clk *pll11k_clk, u64 ratio)  in fsl_asoc_reparent_pll_clocks()
125 	struct clk *p, *pll = NULL, *npll = NULL;  in fsl_asoc_reparent_pll_clocks()
129 	if (!clk || !pll8k_clk || !pll11k_clk)  in fsl_asoc_reparent_pll_clocks()
132 	p = clk;  in fsl_asoc_reparent_pll_clocks()
134 		struct clk *pp = clk_get_parent(p);  in fsl_asoc_reparent_pll_clocks()
156  * fsl_asoc_constrain_rates - constrain rates according to clocks
169 			      struct clk *pll8k_clk, struct clk *pll11k_clk,  in fsl_asoc_constrain_rates()
170 			      struct clk *ext_clk, int *target_rates)  in fsl_asoc_constrain_rates()
177 		target_constr->list = target_rates;  in fsl_asoc_constrain_rates()
178 		target_constr->count = 0;  in fsl_asoc_constrain_rates()
179 		for (i = 0; i < original_constr->count; i++) {  in fsl_asoc_constrain_rates()
185 				    do_div(clk_rate[j], original_constr->list[i]) == 0) {  in fsl_asoc_constrain_rates()
186 					target_rates[k++] = original_constr->list[i];  in fsl_asoc_constrain_rates()
187 					target_constr->count++;  in fsl_asoc_constrain_rates()
194 		if (!target_constr->count)  in fsl_asoc_constrain_rates()