Lines Matching +full:imx35 +full:- +full:spdif
1 // SPDX-License-Identifier: GPL-2.0
25 #include "imx-pcm.h"
72 * SPDIF control structure
97 * struct fsl_spdif_priv - Freescale SPDIF private data
98 * @soc: SPDIF soc data
99 * @fsl_spdif_control: SPDIF control data
214 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) in fsl_spdif_can_set_clk_rate() argument
216 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; in fsl_spdif_can_set_clk_rate()
222 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_dpll_lock()
223 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_dpll_lock()
229 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", in spdif_irq_dpll_lock()
232 spdif_priv->dpll_locked = locked ? true : false; in spdif_irq_dpll_lock()
234 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) { in spdif_irq_dpll_lock()
235 snd_ctl_notify(spdif_priv->snd_card, in spdif_irq_dpll_lock()
237 &spdif_priv->rxrate_kcontrol->id); in spdif_irq_dpll_lock()
244 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_sym_error()
245 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_sym_error()
247 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); in spdif_irq_sym_error()
250 if (!spdif_priv->dpll_locked) in spdif_irq_sym_error()
257 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uqrx_full()
258 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uqrx_full()
259 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uqrx_full()
264 pos = &ctrl->upos; in spdif_irq_uqrx_full()
269 pos = &ctrl->qpos; in spdif_irq_uqrx_full()
274 dev_err(&pdev->dev, "unsupported channel name\n"); in spdif_irq_uqrx_full()
278 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); in spdif_irq_uqrx_full()
283 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); in spdif_irq_uqrx_full()
288 ctrl->subcode[*pos++] = val >> 16; in spdif_irq_uqrx_full()
289 ctrl->subcode[*pos++] = val >> 8; in spdif_irq_uqrx_full()
290 ctrl->subcode[*pos++] = val; in spdif_irq_uqrx_full()
296 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_sync()
297 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_sync()
299 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); in spdif_irq_uq_sync()
302 if (ctrl->qpos == 0) in spdif_irq_uq_sync()
306 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; in spdif_irq_uq_sync()
312 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_err()
313 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uq_err()
314 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_err()
317 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); in spdif_irq_uq_err()
324 ctrl->ready_buf = 0; in spdif_irq_uq_err()
325 ctrl->upos = 0; in spdif_irq_uq_err()
326 ctrl->qpos = 0; in spdif_irq_uq_err()
329 /* Get spdif interrupt status and clear the interrupt */
332 struct regmap *regmap = spdif_priv->regmap; in spdif_intr_status_clear()
346 struct platform_device *pdev = spdif_priv->pdev; in spdif_isr()
355 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); in spdif_isr()
358 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); in spdif_isr()
361 dev_dbg(&pdev->dev, "isr: cstatus new\n"); in spdif_isr()
364 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); in spdif_isr()
370 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); in spdif_isr()
376 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); in spdif_isr()
382 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); in spdif_isr()
391 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); in spdif_isr()
394 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); in spdif_isr()
401 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); in spdif_isr()
405 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); in spdif_isr()
412 struct regmap *regmap = spdif_priv->regmap; in spdif_softreset()
425 } while ((val & SCR_SOFT_RESET) && cycle--); in spdif_softreset()
434 return -EBUSY; in spdif_softreset()
440 ctrl->ch_status[3] &= ~mask; in spdif_set_cstatus()
441 ctrl->ch_status[3] |= cstatus & mask; in spdif_set_cstatus()
446 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_write_channel_status()
447 struct regmap *regmap = spdif_priv->regmap; in spdif_write_channel_status()
448 struct platform_device *pdev = spdif_priv->pdev; in spdif_write_channel_status()
451 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | in spdif_write_channel_status()
452 (bitrev8(ctrl->ch_status[1]) << 8) | in spdif_write_channel_status()
453 bitrev8(ctrl->ch_status[2]); in spdif_write_channel_status()
456 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); in spdif_write_channel_status()
458 ch_status = bitrev8(ctrl->ch_status[3]) << 16; in spdif_write_channel_status()
461 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); in spdif_write_channel_status()
463 if (spdif_priv->soc->cchannel_192b) { in spdif_write_channel_status()
464 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) | in spdif_write_channel_status()
465 (bitrev8(ctrl->ch_status[1]) << 16) | in spdif_write_channel_status()
466 (bitrev8(ctrl->ch_status[2]) << 8) | in spdif_write_channel_status()
467 bitrev8(ctrl->ch_status[3]); in spdif_write_channel_status()
481 /* Set SPDIF PhaseConfig register for rx clock */
485 struct regmap *regmap = spdif_priv->regmap; in spdif_set_rx_clksrc()
486 u8 clksrc = spdif_priv->rxclk_src; in spdif_set_rx_clksrc()
489 return -EINVAL; in spdif_set_rx_clksrc()
505 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_set_sample_rate()
506 struct regmap *regmap = spdif_priv->regmap; in spdif_set_sample_rate()
507 struct platform_device *pdev = spdif_priv->pdev; in spdif_set_sample_rate()
548 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); in spdif_set_sample_rate()
549 return -EINVAL; in spdif_set_sample_rate()
556 clk = spdif_priv->txclk_src[rate]; in spdif_set_sample_rate()
558 dev_err(&pdev->dev, "tx clock source is out of range\n"); in spdif_set_sample_rate()
559 return -EINVAL; in spdif_set_sample_rate()
562 txclk_df = spdif_priv->txclk_df[rate]; in spdif_set_sample_rate()
564 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); in spdif_set_sample_rate()
565 return -EINVAL; in spdif_set_sample_rate()
568 sysclk_df = spdif_priv->sysclk_df[rate]; in spdif_set_sample_rate()
574 ret = clk_set_rate(spdif_priv->txclk[clk], in spdif_set_sample_rate()
577 dev_err(&pdev->dev, "failed to set tx clock rate\n"); in spdif_set_sample_rate()
582 dev_dbg(&pdev->dev, "expected clock rate = %d\n", in spdif_set_sample_rate()
584 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", in spdif_set_sample_rate()
585 clk_get_rate(spdif_priv->txclk[clk])); in spdif_set_sample_rate()
597 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", in spdif_set_sample_rate()
598 spdif_priv->txrate[rate], sample_rate); in spdif_set_sample_rate()
608 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_startup()
609 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_startup()
617 dev_err(&pdev->dev, "failed to soft reset\n"); in fsl_spdif_startup()
625 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_startup()
639 /* Power up SPDIF module */ in fsl_spdif_startup()
650 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_shutdown()
653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_shutdown()
667 /* Power down SPDIF module only if tx&rx are both inactive */ in fsl_spdif_shutdown()
677 struct platform_device *pdev = spdif_priv->pdev; in spdif_reparent_rootclk()
686 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; in spdif_reparent_rootclk()
690 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, in spdif_reparent_rootclk()
691 spdif_priv->pll11k_clk, sample_rate); in spdif_reparent_rootclk()
704 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_hw_params()
705 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_hw_params()
709 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_hw_params()
712 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", in fsl_spdif_hw_params()
719 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", in fsl_spdif_hw_params()
739 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_trigger()
740 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_spdif_trigger()
760 return -EINVAL; in fsl_spdif_trigger()
767 * FSL SPDIF IEC958 controller(mixer) functions
779 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_spdif_info()
780 uinfo->count = 1; in fsl_spdif_info()
790 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_get()
792 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; in fsl_spdif_pb_get()
793 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; in fsl_spdif_pb_get()
794 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; in fsl_spdif_pb_get()
795 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; in fsl_spdif_pb_get()
805 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_put()
807 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; in fsl_spdif_pb_put()
808 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; in fsl_spdif_pb_put()
809 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; in fsl_spdif_pb_put()
810 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; in fsl_spdif_pb_put()
823 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_capture_get()
828 return -EAGAIN; in fsl_spdif_capture_get()
831 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
832 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
833 ucontrol->value.iec958.status[2] = cstatus & 0xFF; in fsl_spdif_capture_get()
836 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
837 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
838 ucontrol->value.iec958.status[5] = cstatus & 0xFF; in fsl_spdif_capture_get()
855 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_subcode_get()
857 int ret = -EAGAIN; in fsl_spdif_subcode_get()
859 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
860 if (ctrl->ready_buf) { in fsl_spdif_subcode_get()
861 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; in fsl_spdif_subcode_get()
862 memcpy(&ucontrol->value.iec958.subcode[0], in fsl_spdif_subcode_get()
863 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); in fsl_spdif_subcode_get()
866 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
871 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
875 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_spdif_qinfo()
876 uinfo->count = SPDIF_QSUB_SIZE; in fsl_spdif_qinfo()
887 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_qget()
889 int ret = -EAGAIN; in fsl_spdif_qget()
891 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
892 if (ctrl->ready_buf) { in fsl_spdif_qget()
893 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; in fsl_spdif_qget()
894 memcpy(&ucontrol->value.bytes.data[0], in fsl_spdif_qget()
895 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); in fsl_spdif_qget()
898 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
909 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_vbit_get()
913 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; in fsl_spdif_rx_vbit_get()
924 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_get()
929 val = 1 - val; in fsl_spdif_tx_vbit_get()
930 ucontrol->value.integer.value[0] = val; in fsl_spdif_tx_vbit_get()
940 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_put()
941 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; in fsl_spdif_tx_vbit_put()
953 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_rcm_get()
958 ucontrol->value.integer.value[0] = val; in fsl_spdif_rx_rcm_get()
968 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_rcm_put()
969 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); in fsl_spdif_rx_rcm_put()
972 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; in fsl_spdif_rx_rcm_put()
974 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; in fsl_spdif_rx_rcm_put()
987 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; in fsl_spdif_bypass_get()
997 struct snd_soc_card *card = dai->component->card; in fsl_spdif_bypass_put()
998 bool set = (ucontrol->value.integer.value[0] != 0); in fsl_spdif_bypass_put()
999 struct regmap *regmap = priv->regmap; in fsl_spdif_bypass_put()
1004 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); in fsl_spdif_bypass_put()
1006 if (priv->bypass == set) in fsl_spdif_bypass_put()
1010 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); in fsl_spdif_bypass_put()
1011 return -EBUSY; in fsl_spdif_bypass_put()
1014 pm_runtime_get_sync(dai->dev); in fsl_spdif_bypass_put()
1024 /* Power up SPDIF module */ in fsl_spdif_bypass_put()
1027 /* Power down SPDIF module, disable TX */ in fsl_spdif_bypass_put()
1036 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); in fsl_spdif_bypass_put()
1038 priv->bypass = set; in fsl_spdif_bypass_put()
1039 pm_runtime_put_sync(dai->dev); in fsl_spdif_bypass_put()
1048 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in fsl_spdif_rxrate_info()
1049 uinfo->count = 1; in fsl_spdif_rxrate_info()
1050 uinfo->value.integer.min = 16000; in fsl_spdif_rxrate_info()
1051 uinfo->value.integer.max = 192000; in fsl_spdif_rxrate_info()
1060 /* Get RX data clock rate given the SPDIF bus_clk */
1064 struct regmap *regmap = spdif_priv->regmap; in spdif_get_rxclk_rate()
1065 struct platform_device *pdev = spdif_priv->pdev; in spdif_get_rxclk_rate()
1077 busclk_freq = clk_get_rate(spdif_priv->sysclk); in spdif_get_rxclk_rate()
1084 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); in spdif_get_rxclk_rate()
1085 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); in spdif_get_rxclk_rate()
1086 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); in spdif_get_rxclk_rate()
1103 if (spdif_priv->dpll_locked) in fsl_spdif_rxrate_get()
1106 ucontrol->value.integer.value[0] = rate; in fsl_spdif_rxrate_get()
1114 * 0 Non-CD data
1121 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_get()
1125 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; in fsl_spdif_usync_get()
1133 * 0 Non-CD data
1140 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_put()
1141 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; in fsl_spdif_usync_put()
1148 /* FSL SPDIF IEC958 controller defines */
1180 .name = "IEC958 Q-subcode Capture Default",
1189 .name = "IEC958 RX V-Bit Errors",
1197 .name = "IEC958 TX V-Bit",
1253 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, in fsl_spdif_dai_probe()
1254 &spdif_private->dma_params_rx); in fsl_spdif_dai_probe()
1258 if (spdif_private->soc->raw_capture_mode) in fsl_spdif_dai_probe()
1262 spdif_private->snd_card = dai->component->card->snd_card; in fsl_spdif_dai_probe()
1263 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card, in fsl_spdif_dai_probe()
1265 if (!spdif_private->rxrate_kcontrol) in fsl_spdif_dai_probe()
1266 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n", in fsl_spdif_dai_probe()
1270 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, in fsl_spdif_dai_probe()
1286 .stream_name = "CPU-Playback",
1293 .stream_name = "CPU-Capture",
1303 .name = "fsl-spdif",
1307 /* FSL SPDIF REGMAP */
1430 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); in fsl_spdif_txclk_caldiv()
1454 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1455 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1456 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1460 sub = (u64)(arate - rate[index]) * 100000; in fsl_spdif_txclk_caldiv()
1465 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1466 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1467 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1470 sub = (u64)(rate[index] - arate) * 100000; in fsl_spdif_txclk_caldiv()
1475 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1476 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1477 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1491 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_probe_txclk()
1492 struct device *dev = &pdev->dev; in fsl_spdif_probe_txclk()
1498 clk = spdif_priv->txclk[i]; in fsl_spdif_probe_txclk()
1512 spdif_priv->txclk_src[index] = i; in fsl_spdif_probe_txclk()
1520 spdif_priv->txclk_src[index], rate[index]); in fsl_spdif_probe_txclk()
1522 spdif_priv->txclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1523 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk)) in fsl_spdif_probe_txclk()
1525 spdif_priv->sysclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1527 rate[index], spdif_priv->txrate[index]); in fsl_spdif_probe_txclk()
1541 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); in fsl_spdif_probe()
1543 return -ENOMEM; in fsl_spdif_probe()
1545 spdif_priv->pdev = pdev; in fsl_spdif_probe()
1547 spdif_priv->soc = of_device_get_match_data(&pdev->dev); in fsl_spdif_probe()
1550 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); in fsl_spdif_probe()
1551 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); in fsl_spdif_probe()
1552 spdif_priv->cpu_dai_drv.playback.formats = in fsl_spdif_probe()
1553 spdif_priv->soc->tx_formats; in fsl_spdif_probe()
1560 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); in fsl_spdif_probe()
1561 if (IS_ERR(spdif_priv->regmap)) { in fsl_spdif_probe()
1562 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_spdif_probe()
1563 return PTR_ERR(spdif_priv->regmap); in fsl_spdif_probe()
1566 for (i = 0; i < spdif_priv->soc->interrupts; i++) { in fsl_spdif_probe()
1571 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, in fsl_spdif_probe()
1572 dev_name(&pdev->dev), spdif_priv); in fsl_spdif_probe()
1574 dev_err(&pdev->dev, "could not claim irq %u\n", irq); in fsl_spdif_probe()
1581 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp); in fsl_spdif_probe()
1582 if (IS_ERR(spdif_priv->txclk[i])) { in fsl_spdif_probe()
1583 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i); in fsl_spdif_probe()
1584 return PTR_ERR(spdif_priv->txclk[i]); in fsl_spdif_probe()
1589 spdif_priv->sysclk = spdif_priv->txclk[5]; in fsl_spdif_probe()
1590 if (IS_ERR(spdif_priv->sysclk)) { in fsl_spdif_probe()
1591 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); in fsl_spdif_probe()
1592 return PTR_ERR(spdif_priv->sysclk); in fsl_spdif_probe()
1596 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1597 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1598 dev_err(&pdev->dev, "no core clock in devicetree\n"); in fsl_spdif_probe()
1599 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1602 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); in fsl_spdif_probe()
1603 if (IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_probe()
1604 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); in fsl_spdif_probe()
1607 spdif_priv->rxclk = spdif_priv->txclk[1]; in fsl_spdif_probe()
1608 if (IS_ERR(spdif_priv->rxclk)) { in fsl_spdif_probe()
1609 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); in fsl_spdif_probe()
1610 return PTR_ERR(spdif_priv->rxclk); in fsl_spdif_probe()
1612 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; in fsl_spdif_probe()
1614 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, in fsl_spdif_probe()
1615 &spdif_priv->pll11k_clk); in fsl_spdif_probe()
1618 ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_probe()
1619 spin_lock_init(&ctrl->ctl_lock); in fsl_spdif_probe()
1622 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | in fsl_spdif_probe()
1624 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; in fsl_spdif_probe()
1625 ctrl->ch_status[2] = 0x00; in fsl_spdif_probe()
1626 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | in fsl_spdif_probe()
1629 spdif_priv->dpll_locked = false; in fsl_spdif_probe()
1631 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; in fsl_spdif_probe()
1632 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; in fsl_spdif_probe()
1633 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; in fsl_spdif_probe()
1634 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; in fsl_spdif_probe()
1637 dev_set_drvdata(&pdev->dev, spdif_priv); in fsl_spdif_probe()
1638 pm_runtime_enable(&pdev->dev); in fsl_spdif_probe()
1639 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_probe()
1647 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); in fsl_spdif_probe()
1651 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, in fsl_spdif_probe()
1652 &spdif_priv->cpu_dai_drv, 1); in fsl_spdif_probe()
1654 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); in fsl_spdif_probe()
1661 pm_runtime_disable(&pdev->dev); in fsl_spdif_probe()
1667 pm_runtime_disable(&pdev->dev); in fsl_spdif_remove()
1676 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); in fsl_spdif_runtime_suspend()
1678 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_suspend()
1679 &spdif_priv->regcache_srpc); in fsl_spdif_runtime_suspend()
1680 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_runtime_suspend()
1683 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_suspend()
1685 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_suspend()
1686 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_suspend()
1687 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1698 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1704 if (!IS_ERR(spdif_priv->spbaclk)) { in fsl_spdif_runtime_resume()
1705 ret = clk_prepare_enable(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1713 ret = clk_prepare_enable(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1718 regcache_cache_only(spdif_priv->regmap, false); in fsl_spdif_runtime_resume()
1719 regcache_mark_dirty(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1721 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_resume()
1723 spdif_priv->regcache_srpc); in fsl_spdif_runtime_resume()
1725 ret = regcache_sync(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1732 for (i--; i >= 0; i--) in fsl_spdif_runtime_resume()
1733 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1734 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_resume()
1735 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1737 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1749 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1750 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1751 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1752 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1753 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
1754 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
1761 .name = "fsl-spdif-dai",
1774 MODULE_ALIAS("platform:fsl-spdif-dai");