50 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
56 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
63 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
64 	0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
65 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
66 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
70 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
71 	0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
72 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
73 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
78  * clk_map_imx8qm[0] is for i.MX8QM asrc0
80  * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
85 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
86 	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
87 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
90 	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
91 	0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
92 	0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
98 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
99 	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
100 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
103 	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
104 	0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
105 	0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
133 		*div = 0;  in fsl_asrc_divider_avail()
135 	if (clk_rate == 0 || rate == 0)  in fsl_asrc_divider_avail()
144 	if (rem != 0)  in fsl_asrc_divider_avail()
147 	for (i = 0; i < DIVIDER_NUM; i++) {  in fsl_asrc_divider_avail()
177 	/* select pre_proc between [0, 2] */  in fsl_asrc_sel_proc()
186 		*pre_proc = 0;  in fsl_asrc_sel_proc()
200 		*post_proc = 0;  in fsl_asrc_sel_proc()
220 	int i, ret = 0;  in fsl_asrc_request_pair()
266 			   ASRCTR_ASRCEi_MASK(index), 0);  in fsl_asrc_release_pair()
272 	pair->error = 0;  in fsl_asrc_release_pair()
308 	/* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */  in fsl_asrc_cal_asrck_divisor()
309 	for (ps = 0; div > 8; ps++)  in fsl_asrc_cal_asrck_divisor()
358 	return 0;  in fsl_asrc_set_ideal_ratio()
439 	for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)  in fsl_asrc_config_pair()
448 	for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)  in fsl_asrc_config_pair()
481 	if (div[IN] == 0 || (!ideal && !div_avail)) {  in fsl_asrc_config_pair()
497 	if (div[OUT] == 0 || (!ideal && !div_avail)) {  in fsl_asrc_config_pair()
520 			   ASRCTR_USRi_MASK(index), 0);  in fsl_asrc_config_pair()
554 		return 0;  in fsl_asrc_config_pair()
558 			   ASRCTR_ATSi_MASK(index), 0);  in fsl_asrc_config_pair()
605 	for (i = 0; i < pair->channels * 4; i++)  in fsl_asrc_start_pair()
606 		regmap_write(asrc->regmap, REG_ASRDI(index), 0);  in fsl_asrc_start_pair()
623 			   ASRCTR_ASRCEi_MASK(index), 0);  in fsl_asrc_stop_pair()
651 		snd_pcm_hw_constraint_step(substream->runtime, 0,  in fsl_asrc_dai_startup()
655 	return snd_pcm_hw_constraint_list(substream->runtime, 0,  in fsl_asrc_dai_startup()
675 	for (j = 0; j < 2; j++) {  in fsl_asrc_select_clk()
676 		for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {  in fsl_asrc_select_clk()
744 	return 0;  in fsl_asrc_dai_hw_params()
756 	return 0;  in fsl_asrc_dai_hw_free()
780 	return 0;  in fsl_asrc_dai_trigger()
790 	return 0;  in fsl_asrc_dai_probe()
934 	{ REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
935 	{ REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
936 	{ REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
937 	{ REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
938 	{ REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
939 	{ REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
940 	{ REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
941 	{ REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
942 	{ REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
943 	{ REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
944 	{ REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
945 	{ REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
946 	{ REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
947 	{ REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
948 	{ REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
949 	{ REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
950 	{ REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
951 	{ REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
952 	{ REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
953 	{ REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
954 	{ REG_ASRMCR1C, 0x0000 },
983 	regmap_write(asrc->regmap, REG_ASRIER, 0x0);  in fsl_asrc_init()
986 	regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);  in fsl_asrc_init()
987 	regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);  in fsl_asrc_init()
988 	regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);  in fsl_asrc_init()
989 	regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);  in fsl_asrc_init()
990 	regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);  in fsl_asrc_init()
992 	/* Base address for task queue FIFO. Set to 0x7C */  in fsl_asrc_init()
994 			   ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));  in fsl_asrc_init()
999 	 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947  in fsl_asrc_init()
1107 	return 0;  in fsl_asrc_m2m_prepare()
1114 		pair->first_convert = 0;  in fsl_asrc_m2m_start()
1129 	return 0;  in fsl_asrc_m2m_start()
1139 	return 0;  in fsl_asrc_m2m_stop()
1184 	return 0;  in fsl_asrc_m2m_get_cap()
1192 	for (i = 0; i < pair->channels * 4; i++)  in fsl_asrc_m2m_pair_resume()
1193 		regmap_write(asrc->regmap, REG_ASRDI(pair->index), 0);  in fsl_asrc_m2m_pair_resume()
1196 	return 0;  in fsl_asrc_m2m_pair_resume()
1210 	u32 asrc_fmt = 0;  in fsl_asrc_probe()
1227 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in fsl_asrc_probe()
1239 	irq = platform_get_irq(pdev, 0);  in fsl_asrc_probe()
1240 	if (irq < 0)  in fsl_asrc_probe()
1243 	ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,  in fsl_asrc_probe()
1266 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {  in fsl_asrc_probe()
1367 	if (ret < 0)  in fsl_asrc_probe()
1377 	if (ret < 0 && ret != -ENOSYS)  in fsl_asrc_probe()
1393 	return 0;  in fsl_asrc_probe()
1433 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {  in fsl_asrc_runtime_resume()
1442 			   ASRCTR_ASRCEi_ALL_MASK, 0);  in fsl_asrc_runtime_resume()
1461 		reg = (reg >> ASRCFG_INIRQi_SHIFT(0)) & 0x7;  in fsl_asrc_runtime_resume()
1462 	} while ((reg != ((asrctr >> ASRCTR_ASRCEi_SHIFT(0)) & 0x7)) && --retry);  in fsl_asrc_runtime_resume()
1475 	return 0;  in fsl_asrc_runtime_resume()
1478 	for (i--; i >= 0; i--)  in fsl_asrc_runtime_resume()
1500 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++)  in fsl_asrc_runtime_suspend()
1507 	return 0;  in fsl_asrc_runtime_suspend()