2  * ALSA SoC Synopsys I2S Audio Layer
47 			i2s_write_reg(dev->i2s_base, TER(i), 0);  in i2s_disable_channels()
50 			i2s_write_reg(dev->i2s_base, RER(i), 0);  in i2s_disable_channels()
60 			i2s_read_reg(dev->i2s_base, TOR(i));  in i2s_clear_irqs()
63 			i2s_read_reg(dev->i2s_base, ROR(i));  in i2s_clear_irqs()
74 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_disable_irqs()
75 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);  in i2s_disable_irqs()
79 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_disable_irqs()
80 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);  in i2s_disable_irqs()
92 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_enable_irqs()
93 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);  in i2s_enable_irqs()
97 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_enable_irqs()
98 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);  in i2s_enable_irqs()
111 		isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));  in i2s_irq_handler()
121 		if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {  in i2s_irq_handler()
130 		if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {  in i2s_irq_handler()
137 			dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);  in i2s_irq_handler()
143 			dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);  in i2s_irq_handler()
156 	u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);  in i2s_enable_dma()
164 	i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);  in i2s_enable_dma()
169 	u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);  in i2s_disable_dma()
174 		i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1);  in i2s_disable_dma()
177 		i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1);  in i2s_disable_dma()
179 	i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);  in i2s_disable_dma()
185 	struct i2s_clk_config_data *config = &dev->config;  in i2s_start()
189 	if (dev->tdm_slots) {  in i2s_start()
190 		reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT;  in i2s_start()
192 		reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT;  in i2s_start()
195 	i2s_write_reg(dev->i2s_base, IER, reg);  in i2s_start()
197 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in i2s_start()
198 		i2s_write_reg(dev->i2s_base, ITER, 1);  in i2s_start()
200 		i2s_write_reg(dev->i2s_base, IRER, 1);  in i2s_start()
202 	if (!(dev->use_pio || dev->is_jh7110))  in i2s_start()
203 		i2s_enable_dma(dev, substream->stream);  in i2s_start()
205 	i2s_enable_irqs(dev, substream->stream, config->chan_nr);  in i2s_start()
206 	i2s_write_reg(dev->i2s_base, CER, 1);  in i2s_start()
213 	i2s_clear_irqs(dev, substream->stream);  in i2s_stop()
214 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in i2s_stop()
215 		i2s_write_reg(dev->i2s_base, ITER, 0);  in i2s_stop()
217 		i2s_write_reg(dev->i2s_base, IRER, 0);  in i2s_stop()
219 	if (!(dev->use_pio || dev->is_jh7110))  in i2s_stop()
220 		i2s_disable_dma(dev, substream->stream);  in i2s_stop()
222 	i2s_disable_irqs(dev, substream->stream, 8);  in i2s_stop()
225 	if (!dev->active) {  in i2s_stop()
226 		i2s_write_reg(dev->i2s_base, CER, 0);  in i2s_stop()
227 		i2s_write_reg(dev->i2s_base, IER, 0);  in i2s_stop()
236 	if (dev->is_jh7110) {  in dw_i2s_startup()
238 		struct snd_soc_dai_link *dai_link = rtd->dai_link;  in dw_i2s_startup()
240 		dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC;  in dw_i2s_startup()
249 	struct i2s_clk_config_data *config = &dev->config;  in dw_i2s_config()
254 	for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {  in dw_i2s_config()
256 			i2s_write_reg(dev->i2s_base, TCR(ch_reg),  in dw_i2s_config()
257 				      dev->xfer_resolution);  in dw_i2s_config()
258 			i2s_write_reg(dev->i2s_base, TFCR(ch_reg),  in dw_i2s_config()
259 				      dev->fifo_th - 1);  in dw_i2s_config()
260 			i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |  in dw_i2s_config()
261 				      dev->tdm_mask << TER_TXSLOT_SHIFT);  in dw_i2s_config()
263 			i2s_write_reg(dev->i2s_base, RCR(ch_reg),  in dw_i2s_config()
264 				      dev->xfer_resolution);  in dw_i2s_config()
265 			i2s_write_reg(dev->i2s_base, RFCR(ch_reg),  in dw_i2s_config()
266 				      dev->fifo_th - 1);  in dw_i2s_config()
267 			i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |  in dw_i2s_config()
268 				      dev->tdm_mask << RER_RXSLOT_SHIFT);  in dw_i2s_config()
278 	struct i2s_clk_config_data *config = &dev->config;  in dw_i2s_hw_params()
283 		config->data_width = 16;  in dw_i2s_hw_params()
284 		dev->ccr = 0x00;  in dw_i2s_hw_params()
285 		dev->xfer_resolution = 0x02;  in dw_i2s_hw_params()
289 		config->data_width = 24;  in dw_i2s_hw_params()
290 		dev->ccr = 0x08;  in dw_i2s_hw_params()
291 		dev->xfer_resolution = 0x04;  in dw_i2s_hw_params()
295 		config->data_width = 32;  in dw_i2s_hw_params()
296 		dev->ccr = 0x10;  in dw_i2s_hw_params()
297 		dev->xfer_resolution = 0x05;  in dw_i2s_hw_params()
301 		dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");  in dw_i2s_hw_params()
302 		return -EINVAL;  in dw_i2s_hw_params()
305 	if (dev->tdm_slots)  in dw_i2s_hw_params()
306 		config->data_width = 32;  in dw_i2s_hw_params()
308 	config->chan_nr = params_channels(params);  in dw_i2s_hw_params()
310 	switch (config->chan_nr) {  in dw_i2s_hw_params()
317 		dev_err(dev->dev, "channel not supported\n");  in dw_i2s_hw_params()
318 		return -EINVAL;  in dw_i2s_hw_params()
321 	dw_i2s_config(dev, substream->stream);  in dw_i2s_hw_params()
323 	i2s_write_reg(dev->i2s_base, CCR, dev->ccr);  in dw_i2s_hw_params()
325 	config->sample_rate = params_rate(params);  in dw_i2s_hw_params()
327 	if (dev->capability & DW_I2S_MASTER) {  in dw_i2s_hw_params()
328 		if (dev->i2s_clk_cfg) {  in dw_i2s_hw_params()
329 			ret = dev->i2s_clk_cfg(config);  in dw_i2s_hw_params()
331 				dev_err(dev->dev, "runtime audio clk config fail\n");  in dw_i2s_hw_params()
335 			u32 bitclk = config->sample_rate *  in dw_i2s_hw_params()
336 					config->data_width * 2;  in dw_i2s_hw_params()
338 			ret = clk_set_rate(dev->clk, bitclk);  in dw_i2s_hw_params()
340 				dev_err(dev->dev, "Can't set I2S clock rate: %d\n",  in dw_i2s_hw_params()
354 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in dw_i2s_prepare()
355 		i2s_write_reg(dev->i2s_base, TXFFR, 1);  in dw_i2s_prepare()
357 		i2s_write_reg(dev->i2s_base, RXFFR, 1);  in dw_i2s_prepare()
372 		dev->active++;  in dw_i2s_trigger()
379 		dev->active--;  in dw_i2s_trigger()
383 		ret = -EINVAL;  in dw_i2s_trigger()
396 		if (dev->capability & DW_I2S_SLAVE)  in dw_i2s_set_fmt()
399 			ret = -EINVAL;  in dw_i2s_set_fmt()
402 		if (dev->capability & DW_I2S_MASTER)  in dw_i2s_set_fmt()
405 			ret = -EINVAL;  in dw_i2s_set_fmt()
409 		ret = -EINVAL;  in dw_i2s_set_fmt()
412 		dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");  in dw_i2s_set_fmt()
413 		ret = -EINVAL;  in dw_i2s_set_fmt()
423 		dev->frame_offset = 1;  in dw_i2s_set_fmt()
426 		dev->frame_offset = 0;  in dw_i2s_set_fmt()
429 		dev_err(dev->dev, "DAI format unsupported");  in dw_i2s_set_fmt()
430 		return -EINVAL;  in dw_i2s_set_fmt()
442 		return -EINVAL;  in dw_i2s_set_tdm_slot()
445 		return -EINVAL;  in dw_i2s_set_tdm_slot()
448 		return -EINVAL;  in dw_i2s_set_tdm_slot()
451 		return -EINVAL;  in dw_i2s_set_tdm_slot()
453 	dev->tdm_slots = slots;  in dw_i2s_set_tdm_slot()
454 	dev->tdm_mask = rx_mask;  in dw_i2s_set_tdm_slot()
456 	dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1);  in dw_i2s_set_tdm_slot()
457 	dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1);  in dw_i2s_set_tdm_slot()
466 	snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);  in dw_i2s_dai_probe()
485 	if (dw_dev->capability & DW_I2S_MASTER)  in dw_i2s_runtime_suspend()
486 		clk_disable(dw_dev->clk);  in dw_i2s_runtime_suspend()
495 	if (dw_dev->capability & DW_I2S_MASTER) {  in dw_i2s_runtime_resume()
496 		ret = clk_enable(dw_dev->clk);  in dw_i2s_runtime_resume()
507 	if (dev->capability & DW_I2S_MASTER)  in dw_i2s_suspend()
508 		clk_disable(dev->clk);  in dw_i2s_suspend()
518 	if (dev->capability & DW_I2S_MASTER) {  in dw_i2s_resume()
519 		ret = clk_enable(dev->clk);  in dw_i2s_resume()
539 	.name			= "dw-i2s",
547  * defined in the I2S block's configuration in terms of sound system
549  * according to the number of configuration bits describing an I2S
553 /* Maximum bit resolution of a channel - not uniformly spaced */
584 	 * the I2S block's configuration.  in dw_configure_dai()
586 	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);  in dw_configure_dai()
587 	u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);  in dw_configure_dai()
591 	if (dev->capability & DWC_I2S_RECORD &&  in dw_configure_dai()
592 			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)  in dw_configure_dai()
595 	if (dev->capability & DWC_I2S_PLAY &&  in dw_configure_dai()
596 			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)  in dw_configure_dai()
600 		dev_dbg(dev->dev, " designware: play supported\n");  in dw_configure_dai()
603 			return -EINVAL;  in dw_configure_dai()
604 		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)  in dw_configure_dai()
606 		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;  in dw_configure_dai()
607 		dw_i2s_dai->playback.channels_max =  in dw_configure_dai()
609 		dw_i2s_dai->playback.formats = formats[idx];  in dw_configure_dai()
610 		dw_i2s_dai->playback.rates = rates;  in dw_configure_dai()
614 		dev_dbg(dev->dev, "designware: record supported\n");  in dw_configure_dai()
617 			return -EINVAL;  in dw_configure_dai()
618 		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)  in dw_configure_dai()
620 		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;  in dw_configure_dai()
621 		dw_i2s_dai->capture.channels_max =  in dw_configure_dai()
623 		dw_i2s_dai->capture.formats = formats[idx];  in dw_configure_dai()
624 		dw_i2s_dai->capture.rates = rates;  in dw_configure_dai()
628 		dev_dbg(dev->dev, "designware: i2s master mode supported\n");  in dw_configure_dai()
629 		dev->capability |= DW_I2S_MASTER;  in dw_configure_dai()
631 		dev_dbg(dev->dev, "designware: i2s slave mode supported\n");  in dw_configure_dai()
632 		dev->capability |= DW_I2S_SLAVE;  in dw_configure_dai()
635 	dev->fifo_th = fifo_depth / 2;  in dw_configure_dai()
644 	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);  in dw_configure_dai_by_pd()
649 		return -EINVAL;  in dw_configure_dai_by_pd()
651 	ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);  in dw_configure_dai_by_pd()
655 	if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)  in dw_configure_dai_by_pd()
658 	if (dev->is_jh7110) {  in dw_configure_dai_by_pd()
660 		u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);  in dw_configure_dai_by_pd()
665 			dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;  in dw_configure_dai_by_pd()
666 			dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 *  in dw_configure_dai_by_pd()
668 			dev->play_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_pd()
672 			dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;  in dw_configure_dai_by_pd()
673 			dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 *  in dw_configure_dai_by_pd()
675 			dev->capture_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_pd()
679 		dev->play_dma_data.pd.data = pdata->play_dma_data;  in dw_configure_dai_by_pd()
680 		dev->capture_dma_data.pd.data = pdata->capture_dma_data;  in dw_configure_dai_by_pd()
681 		dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;  in dw_configure_dai_by_pd()
682 		dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;  in dw_configure_dai_by_pd()
683 		dev->play_dma_data.pd.max_burst = 16;  in dw_configure_dai_by_pd()
684 		dev->capture_dma_data.pd.max_burst = 16;  in dw_configure_dai_by_pd()
685 		dev->play_dma_data.pd.addr_width = bus_widths[idx];  in dw_configure_dai_by_pd()
686 		dev->capture_dma_data.pd.addr_width = bus_widths[idx];  in dw_configure_dai_by_pd()
687 		dev->play_dma_data.pd.filter = pdata->filter;  in dw_configure_dai_by_pd()
688 		dev->capture_dma_data.pd.filter = pdata->filter;  in dw_configure_dai_by_pd()
698 	u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);  in dw_configure_dai_by_dt()
699 	u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);  in dw_configure_dai_by_dt()
711 		dev->capability |= DWC_I2S_PLAY;  in dw_configure_dai_by_dt()
712 		dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;  in dw_configure_dai_by_dt()
713 		dev->play_dma_data.dt.fifo_size = fifo_depth *  in dw_configure_dai_by_dt()
715 		dev->play_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_dt()
720 		dev->capability |= DWC_I2S_RECORD;  in dw_configure_dai_by_dt()
721 		dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;  in dw_configure_dai_by_dt()
722 		dev->capture_dma_data.dt.fifo_size = fifo_depth *  in dw_configure_dai_by_dt()
724 		dev->capture_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_dt()
742 	struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);  in jh7110_i2s_crg_master_init()
751 		return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");  in jh7110_i2s_crg_master_init()
753 	ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);  in jh7110_i2s_crg_master_init()
755 		return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");  in jh7110_i2s_crg_master_init()
789 	dev->is_jh7110 = true;  in jh7110_i2s_crg_master_init()
816 	struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);  in jh7110_i2s_crg_slave_init()
829 		return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");  in jh7110_i2s_crg_slave_init()
831 	ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);  in jh7110_i2s_crg_slave_init()
833 		return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");  in jh7110_i2s_crg_slave_init()
877 	dev->is_jh7110 = true;  in jh7110_i2s_crg_slave_init()
896 	regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node,  in jh7110_i2srx_crg_init()
900 		return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n");  in jh7110_i2srx_crg_init()
911 	u32 bclk_rate = config->sample_rate * 64;  in jh7110_i2stx0_clk_cfg()
913 	return clk_set_rate(dev->clk, bclk_rate);  in jh7110_i2stx0_clk_cfg()
919 	const struct i2s_platform_data *pdata = pdev->dev.platform_data;  in dw_i2s_probe()
926 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);  in dw_i2s_probe()
928 		return -ENOMEM;  in dw_i2s_probe()
930 	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);  in dw_i2s_probe()
932 		return -ENOMEM;  in dw_i2s_probe()
934 	dw_i2s_dai->ops = &dw_i2s_dai_ops;  in dw_i2s_probe()
936 	dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in dw_i2s_probe()
937 	if (IS_ERR(dev->i2s_base))  in dw_i2s_probe()
938 		return PTR_ERR(dev->i2s_base);  in dw_i2s_probe()
940 	dev->dev = &pdev->dev;  in dw_i2s_probe()
941 	dev->is_jh7110 = false;  in dw_i2s_probe()
943 		if (pdata->i2s_pd_init) {  in dw_i2s_probe()
944 			ret = pdata->i2s_pd_init(dev);  in dw_i2s_probe()
950 	if (!dev->is_jh7110) {  in dw_i2s_probe()
951 		dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev);  in dw_i2s_probe()
952 		if (IS_ERR(dev->reset))  in dw_i2s_probe()
953 			return PTR_ERR(dev->reset);  in dw_i2s_probe()
955 		ret = reset_control_deassert(dev->reset);  in dw_i2s_probe()
962 		ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,  in dw_i2s_probe()
963 				pdev->name, dev);  in dw_i2s_probe()
965 			dev_err(&pdev->dev, "failed to request irq\n");  in dw_i2s_probe()
970 	dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;  in dw_i2s_probe()
971 	dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;  in dw_i2s_probe()
973 		dev->capability = pdata->cap;  in dw_i2s_probe()
975 		dev->quirks = pdata->quirks;  in dw_i2s_probe()
976 		if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {  in dw_i2s_probe()
977 			dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;  in dw_i2s_probe()
978 			dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;  in dw_i2s_probe()
988 	if (dev->capability & DW_I2S_MASTER) {  in dw_i2s_probe()
990 			dev->i2s_clk_cfg = pdata->i2s_clk_cfg;  in dw_i2s_probe()
991 			if (!dev->i2s_clk_cfg) {  in dw_i2s_probe()
992 				dev_err(&pdev->dev, "no clock configure method\n");  in dw_i2s_probe()
993 				ret = -ENODEV;  in dw_i2s_probe()
997 		dev->clk = devm_clk_get_enabled(&pdev->dev, clk_id);  in dw_i2s_probe()
999 		if (IS_ERR(dev->clk)) {  in dw_i2s_probe()
1000 			ret = PTR_ERR(dev->clk);  in dw_i2s_probe()
1005 	dev_set_drvdata(&pdev->dev, dev);  in dw_i2s_probe()
1006 	ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,  in dw_i2s_probe()
1009 		dev_err(&pdev->dev, "not able to register dai\n");  in dw_i2s_probe()
1013 	if (!pdata || dev->is_jh7110) {  in dw_i2s_probe()
1016 			dev->use_pio = true;  in dw_i2s_probe()
1017 			dev->l_reg = LRBR_LTHR(0);  in dw_i2s_probe()
1018 			dev->r_reg = RRBR_RTHR(0);  in dw_i2s_probe()
1020 			ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,  in dw_i2s_probe()
1022 			dev->use_pio = false;  in dw_i2s_probe()
1026 			dev_err(&pdev->dev, "could not register pcm: %d\n",  in dw_i2s_probe()
1032 	pm_runtime_enable(&pdev->dev);  in dw_i2s_probe()
1036 	reset_control_assert(dev->reset);  in dw_i2s_probe()
1042 	struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);  in dw_i2s_remove()
1044 	reset_control_assert(dev->reset);  in dw_i2s_remove()
1045 	pm_runtime_disable(&pdev->dev);  in dw_i2s_remove()
1075 	{ .compatible = "snps,designware-i2s",	 },
1076 	{ .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, },
1077 	{ .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,},
1078 	{ .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,},
1093 		.name	= "designware-i2s",
1102 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");