Lines Matching +full:0 +full:- +full:128
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
12 * and mono/stereo Class-D speaker driver.
36 #include <dt-bindings/sound/tlv320aic31xx.h>
44 { AIC31XX_CLKMUX, 0x00 },
45 { AIC31XX_PLLPR, 0x11 },
46 { AIC31XX_PLLJ, 0x04 },
47 { AIC31XX_PLLDMSB, 0x00 },
48 { AIC31XX_PLLDLSB, 0x00 },
49 { AIC31XX_NDAC, 0x01 },
50 { AIC31XX_MDAC, 0x01 },
51 { AIC31XX_DOSRMSB, 0x00 },
52 { AIC31XX_DOSRLSB, 0x80 },
53 { AIC31XX_NADC, 0x01 },
54 { AIC31XX_MADC, 0x01 },
55 { AIC31XX_AOSR, 0x80 },
56 { AIC31XX_IFACE1, 0x00 },
57 { AIC31XX_DATA_OFFSET, 0x00 },
58 { AIC31XX_IFACE2, 0x00 },
59 { AIC31XX_BCLKN, 0x01 },
60 { AIC31XX_DACSETUP, 0x14 },
61 { AIC31XX_DACMUTE, 0x0c },
62 { AIC31XX_LDACVOL, 0x00 },
63 { AIC31XX_RDACVOL, 0x00 },
64 { AIC31XX_ADCSETUP, 0x00 },
65 { AIC31XX_ADCFGA, 0x80 },
66 { AIC31XX_ADCVOL, 0x00 },
67 { AIC31XX_HPDRIVER, 0x04 },
68 { AIC31XX_SPKAMP, 0x06 },
69 { AIC31XX_DACMIXERROUTE, 0x00 },
70 { AIC31XX_LANALOGHPL, 0x7f },
71 { AIC31XX_RANALOGHPR, 0x7f },
72 { AIC31XX_LANALOGSPL, 0x7f },
73 { AIC31XX_RANALOGSPR, 0x7f },
74 { AIC31XX_HPLGAIN, 0x02 },
75 { AIC31XX_HPRGAIN, 0x02 },
76 { AIC31XX_SPLGAIN, 0x00 },
77 { AIC31XX_SPRGAIN, 0x00 },
78 { AIC31XX_MICBIAS, 0x00 },
79 { AIC31XX_MICPGA, 0x80 },
80 { AIC31XX_MICPGAPI, 0x00 },
81 { AIC31XX_MICPGAMI, 0x00 },
123 .range_min = 0,
124 .range_max = 12 * 128,
126 .selector_mask = 0xff,
127 .selector_shift = 0,
128 .window_start = 0,
129 .window_len = 128,
143 .max_register = 12 * 128,
180 u8 ocmv; /* output common-mode voltage */
197 /* ADC dividers can be disabled by configuring them to 0 */
201 { 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2},
202 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
203 {12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
204 {12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2},
206 { 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3},
207 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
208 {12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
209 {12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2},
211 { 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3},
212 { 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3},
213 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
214 {12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
215 {12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2},
217 { 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3},
218 { 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3},
219 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
220 {12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
221 {12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2},
223 { 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2},
224 { 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2},
225 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
226 {12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
227 {12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2},
229 { 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2},
230 { 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2},
231 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
232 {12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
233 {12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2},
235 { 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2},
236 { 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2},
237 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
239 {12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2},
241 { 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2},
242 { 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2},
247 { 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2},
248 { 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2},
253 { 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2},
254 {11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2},
259 { 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2},
260 {12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2},
293 "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",
300 "0ms", "0.98ms", "1.95ms", "3.9ms" };
308 static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,
311 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
312 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
313 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
314 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
315 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
317 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
318 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
325 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
328 AIC31XX_HPRGAIN, 2, 1, 0),
330 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
333 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
335 /* HP de-pop control: apply power not immediately but via ramp
340 SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),
341 SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),
352 0, -24, 40, 6, 0, adc_cgain_tlv),
354 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
355 119, 0, mic_pga_tlv),
360 AIC31XX_SPRGAIN, 2, 1, 0),
362 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
365 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
370 2, 1, 0),
372 3, 3, 0, class_D_drv_tlv),
375 0, 0x7F, 1, sp_vol_tlv),
390 int ret = regmap_read(aic31xx->regmap, reg, &bits); in aic31xx_wait_bits()
394 ret = regmap_read(aic31xx->regmap, reg, &bits); in aic31xx_wait_bits()
395 counter--; in aic31xx_wait_bits()
398 dev_err(aic31xx->dev, in aic31xx_wait_bits()
399 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", in aic31xx_wait_bits()
401 (count - counter) * sleep); in aic31xx_wait_bits()
402 ret = -1; in aic31xx_wait_bits()
412 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in aic31xx_dapm_power_event()
418 switch (WIDGET_BIT(w->reg, w->shift)) { in aic31xx_dapm_power_event()
446 dev_err(component->dev, "Unknown widget '%s' calling %s\n", in aic31xx_dapm_power_event()
447 w->name, __func__); in aic31xx_dapm_power_event()
448 return -EINVAL; in aic31xx_dapm_power_event()
456 return aic31xx_wait_bits(aic31xx, reg, mask, 0, in aic31xx_dapm_power_event()
459 dev_dbg(component->dev, in aic31xx_dapm_power_event()
461 event, w->name); in aic31xx_dapm_power_event()
463 return 0; in aic31xx_dapm_power_event()
467 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
468 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
469 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
473 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
474 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
478 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
479 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
480 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
484 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
485 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
489 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
492 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
495 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
498 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
501 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
504 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
507 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
510 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
515 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in mic_bias_event()
523 aic31xx->micbias_vg << in mic_bias_event()
525 dev_dbg(component->dev, "%s: turned on\n", __func__); in mic_bias_event()
530 AIC31XX_MICBIAS_MASK, 0); in mic_bias_event()
531 dev_dbg(component->dev, "%s: turned off\n", __func__); in mic_bias_event()
534 return 0; in mic_bias_event()
538 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
541 SND_SOC_NOPM, 0, 0, &ldac_in_control),
543 SND_SOC_NOPM, 0, 0, &rdac_in_control),
546 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
550 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
554 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
556 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
560 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
561 NULL, 0, aic31xx_dapm_power_event,
563 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
564 NULL, 0, aic31xx_dapm_power_event,
568 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
572 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
573 NULL, 0),
586 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
589 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
601 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
603 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
605 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
609 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
613 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
618 7, 1, NULL, 0),
621 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
624 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
628 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
632 /* AIC3111 and AIC3110 have stereo class-D amplifier */
633 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
636 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
639 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
641 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
647 /* AIC3100 and AIC3120 have only mono class-D amplifier */
649 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
652 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
695 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
696 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
697 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
698 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
699 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
700 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
701 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
702 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
703 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
705 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
706 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
707 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
709 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
710 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
711 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
712 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
778 int ret = 0; in aic31xx_add_controls()
781 if (!(aic31xx->codec_type & DAC31XX_BIT)) in aic31xx_add_controls()
788 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) in aic31xx_add_controls()
804 int ret = 0; in aic31xx_add_widgets()
806 if (aic31xx->codec_type & DAC31XX_BIT) { in aic31xx_add_widgets()
830 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { in aic31xx_add_widgets()
854 return 0; in aic31xx_add_widgets()
863 int bclk_n = 0; in aic31xx_setup_pll()
864 int match = -1; in aic31xx_setup_pll()
867 if (!aic31xx->sysclk || !aic31xx->p_div) { in aic31xx_setup_pll()
868 dev_err(component->dev, "Master clock not supplied\n"); in aic31xx_setup_pll()
869 return -EINVAL; in aic31xx_setup_pll()
871 mclk_p = aic31xx->sysclk / aic31xx->p_div; in aic31xx_setup_pll()
879 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { in aic31xx_setup_pll()
886 if (s < bclk_score && bn > 0) { in aic31xx_setup_pll()
894 if (match == -1) { in aic31xx_setup_pll()
895 dev_err(component->dev, in aic31xx_setup_pll()
899 return -EINVAL; in aic31xx_setup_pll()
901 if (bclk_score != 0) { in aic31xx_setup_pll()
902 dev_warn(component->dev, "Can not produce exact bitclock"); in aic31xx_setup_pll()
915 (aic31xx->p_div << 4) | aic31xx_divs[i].pll_r); in aic31xx_setup_pll()
921 aic31xx_divs[i].pll_d & 0xff); in aic31xx_setup_pll()
930 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); in aic31xx_setup_pll()
944 aic31xx->rate_div_line = i; in aic31xx_setup_pll()
946 dev_dbg(component->dev, in aic31xx_setup_pll()
950 aic31xx->p_div, in aic31xx_setup_pll()
960 return 0; in aic31xx_setup_pll()
967 struct snd_soc_component *component = dai->component; in aic31xx_hw_params()
969 u8 data = 0; in aic31xx_hw_params()
971 dev_dbg(component->dev, "## %s: width %d rate %d\n", in aic31xx_hw_params()
991 dev_err(component->dev, "%s: Unsupported width %d\n", in aic31xx_hw_params()
993 return -EINVAL; in aic31xx_hw_params()
1004 if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) { in aic31xx_hw_params()
1005 aic31xx->sysclk = params_rate(params) * params_width(params) * in aic31xx_hw_params()
1007 aic31xx->p_div = 1; in aic31xx_hw_params()
1016 struct snd_soc_component *component = codec_dai->component; in aic31xx_dac_mute()
1024 AIC31XX_DACMUTE_MASK, 0x0); in aic31xx_dac_mute()
1027 return 0; in aic31xx_dac_mute()
1039 aic31xx->master_dapm_route_applied) { in aic31xx_clock_master_routes()
1046 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) in aic31xx_clock_master_routes()
1054 aic31xx->master_dapm_route_applied = false; in aic31xx_clock_master_routes()
1056 !aic31xx->master_dapm_route_applied) { in aic31xx_clock_master_routes()
1063 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) in aic31xx_clock_master_routes()
1071 aic31xx->master_dapm_route_applied = true; in aic31xx_clock_master_routes()
1074 return 0; in aic31xx_clock_master_routes()
1080 struct snd_soc_component *component = codec_dai->component; in aic31xx_set_dai_fmt()
1081 u8 iface_reg1 = 0; in aic31xx_set_dai_fmt()
1082 u8 iface_reg2 = 0; in aic31xx_set_dai_fmt()
1083 u8 dsp_a_val = 0; in aic31xx_set_dai_fmt()
1085 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt); in aic31xx_set_dai_fmt()
1100 dev_err(component->dev, "Invalid DAI clock provider\n"); in aic31xx_set_dai_fmt()
1101 return -EINVAL; in aic31xx_set_dai_fmt()
1112 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); in aic31xx_set_dai_fmt()
1113 return -EINVAL; in aic31xx_set_dai_fmt()
1121 dsp_a_val = 0x1; in aic31xx_set_dai_fmt()
1142 dev_err(component->dev, "Invalid DAI interface format\n"); in aic31xx_set_dai_fmt()
1143 return -EINVAL; in aic31xx_set_dai_fmt()
1163 struct snd_soc_component *component = codec_dai->component; in aic31xx_set_dai_sysclk()
1167 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", in aic31xx_set_dai_sysclk()
1174 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", in aic31xx_set_dai_sysclk()
1176 return -EINVAL; in aic31xx_set_dai_sysclk()
1178 aic31xx->p_div = i; in aic31xx_set_dai_sysclk()
1180 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) in aic31xx_set_dai_sysclk()
1181 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) in aic31xx_set_dai_sysclk()
1184 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", in aic31xx_set_dai_sysclk()
1186 return -EINVAL; in aic31xx_set_dai_sysclk()
1193 aic31xx->sysclk_id = clk_id; in aic31xx_set_dai_sysclk()
1194 aic31xx->sysclk = freq; in aic31xx_set_dai_sysclk()
1196 return 0; in aic31xx_set_dai_sysclk()
1204 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; in aic31xx_regulator_event()
1211 if (aic31xx->gpio_reset) in aic31xx_regulator_event()
1212 gpiod_set_value_cansleep(aic31xx->gpio_reset, 1); in aic31xx_regulator_event()
1214 regcache_mark_dirty(aic31xx->regmap); in aic31xx_regulator_event()
1215 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); in aic31xx_regulator_event()
1218 return 0; in aic31xx_regulator_event()
1223 int ret = 0; in aic31xx_reset()
1225 if (aic31xx->gpio_reset) { in aic31xx_reset()
1226 gpiod_set_value_cansleep(aic31xx->gpio_reset, 1); in aic31xx_reset()
1228 gpiod_set_value_cansleep(aic31xx->gpio_reset, 0); in aic31xx_reset()
1230 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); in aic31xx_reset()
1243 dev_dbg(component->dev, "codec clock -> on (rate %d)\n", in aic31xx_clk_on()
1244 aic31xx_divs[aic31xx->rate_div_line].rate); in aic31xx_clk_on()
1249 if (aic31xx_divs[aic31xx->rate_div_line].nadc) in aic31xx_clk_on()
1251 if (aic31xx_divs[aic31xx->rate_div_line].madc) in aic31xx_clk_on()
1259 u8 off = 0; in aic31xx_clk_off()
1261 dev_dbg(component->dev, "codec clock -> off\n"); in aic31xx_clk_off()
1275 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), in aic31xx_power_on()
1276 aic31xx->supplies); in aic31xx_power_on()
1280 regcache_cache_only(aic31xx->regmap, false); in aic31xx_power_on()
1282 /* Reset device registers for a consistent power-on like state */ in aic31xx_power_on()
1284 if (ret < 0) in aic31xx_power_on()
1285 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); in aic31xx_power_on()
1287 ret = regcache_sync(aic31xx->regmap); in aic31xx_power_on()
1289 dev_err(component->dev, in aic31xx_power_on()
1291 regcache_cache_only(aic31xx->regmap, true); in aic31xx_power_on()
1292 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), in aic31xx_power_on()
1293 aic31xx->supplies); in aic31xx_power_on()
1302 aic31xx_set_jack(component, aic31xx->jack, NULL); in aic31xx_power_on()
1304 return 0; in aic31xx_power_on()
1311 regcache_cache_only(aic31xx->regmap, true); in aic31xx_power_off()
1312 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), in aic31xx_power_off()
1313 aic31xx->supplies); in aic31xx_power_off()
1319 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__, in aic31xx_set_bias_level()
1347 return 0; in aic31xx_set_bias_level()
1355 aic31xx->jack = jack; in aic31xx_set_jack()
1358 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT, in aic31xx_set_jack()
1359 jack ? AIC31XX_HSD_ENABLE : 0); in aic31xx_set_jack()
1361 return 0; in aic31xx_set_jack()
1369 dev_dbg(aic31xx->dev, "## %s\n", __func__); in aic31xx_codec_probe()
1371 aic31xx->component = component; in aic31xx_codec_probe()
1373 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { in aic31xx_codec_probe()
1374 aic31xx->disable_nb[i].nb.notifier_call = in aic31xx_codec_probe()
1376 aic31xx->disable_nb[i].aic31xx = aic31xx; in aic31xx_codec_probe()
1378 aic31xx->supplies[i].consumer, in aic31xx_codec_probe()
1379 &aic31xx->disable_nb[i].nb); in aic31xx_codec_probe()
1381 dev_err(component->dev, in aic31xx_codec_probe()
1388 regcache_cache_only(aic31xx->regmap, true); in aic31xx_codec_probe()
1389 regcache_mark_dirty(aic31xx->regmap); in aic31xx_codec_probe()
1399 /* set output common-mode voltage */ in aic31xx_codec_probe()
1402 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT); in aic31xx_codec_probe()
1404 return 0; in aic31xx_codec_probe()
1433 .name = "tlv320dac31xx-hifi",
1448 .name = "tlv320aic31xx-hifi",
1485 { "10TI3100", 0 },
1494 struct device *dev = aic31xx->dev; in aic31xx_irq()
1499 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value); in aic31xx_irq()
1516 int status = 0; in aic31xx_irq()
1518 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2, in aic31xx_irq()
1529 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val); in aic31xx_irq()
1547 if (aic31xx->jack) in aic31xx_irq()
1548 snd_soc_jack_report(aic31xx->jack, status, in aic31xx_irq()
1555 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value); in aic31xx_irq()
1558 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); in aic31xx_irq()
1570 dev_warn(dev, "Left-channel DAC overflow has occurred\n"); in aic31xx_irq()
1572 dev_warn(dev, "Right-channel DAC overflow has occurred\n"); in aic31xx_irq()
1584 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value); in aic31xx_irq()
1595 struct device *dev = priv->dev; in aic31xx_configure_ocmv()
1599 if (dev->fwnode && in aic31xx_configure_ocmv()
1600 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) { in aic31xx_configure_ocmv()
1603 priv->ocmv = value; in aic31xx_configure_ocmv()
1608 avdd = regulator_get_voltage(priv->supplies[3].consumer); in aic31xx_configure_ocmv()
1609 dvdd = regulator_get_voltage(priv->supplies[5].consumer); in aic31xx_configure_ocmv()
1616 priv->ocmv = AIC31XX_HPD_OCMV_1_8V; in aic31xx_configure_ocmv()
1618 priv->ocmv = AIC31XX_HPD_OCMV_1_65V; in aic31xx_configure_ocmv()
1620 priv->ocmv = AIC31XX_HPD_OCMV_1_5V; in aic31xx_configure_ocmv()
1622 priv->ocmv = AIC31XX_HPD_OCMV_1_35V; in aic31xx_configure_ocmv()
1650 * Coefficients firmware binary structure. Multi-byte values are big-endian. in tlv320dac3100_fw_load()
1652 * @0, 16bits: Magic (0xB30C) in tlv320dac3100_fw_load()
1653 * @2, 16bits: Version (0x0100 for version 1.0) in tlv320dac3100_fw_load()
1655 * @5, 62 16-bit values: Page 8 buffer A DAC programmable filter coefficients in tlv320dac3100_fw_load()
1656 * @129, 12 16-bit values: Page 9 Buffer A DAC programmable filter coefficients in tlv320dac3100_fw_load()
1659 * ranging from -32 768 to 32 767. For more details on filter coefficients, in tlv320dac3100_fw_load()
1660 * please refer to the TLV320DAC3100 datasheet, tables 6-120 and 6-123. in tlv320dac3100_fw_load()
1664 dev_err(aic31xx->dev, "firmware size is %zu, expected 153 bytes\n", size); in tlv320dac3100_fw_load()
1665 return -EINVAL; in tlv320dac3100_fw_load()
1670 if (val16 != 0xb30c) { in tlv320dac3100_fw_load()
1671 dev_err(aic31xx->dev, "fw magic is 0x%04x expected 0xb30c\n", val16); in tlv320dac3100_fw_load()
1672 return -EINVAL; in tlv320dac3100_fw_load()
1678 if (val16 != 0x0100) { in tlv320dac3100_fw_load()
1679 dev_err(aic31xx->dev, "invalid firmware version 0x%04x! expected 1", val16); in tlv320dac3100_fw_load()
1680 return -EINVAL; in tlv320dac3100_fw_load()
1684 ret = regmap_write(aic31xx->regmap, AIC31XX_DACPRB, *data); in tlv320dac3100_fw_load()
1686 dev_err(aic31xx->dev, "failed to write PRB index: err %d\n", ret); in tlv320dac3100_fw_load()
1693 ret = regmap_write(aic31xx->regmap, AIC31XX_REG(8, reg), *data); in tlv320dac3100_fw_load()
1695 dev_err(aic31xx->dev, in tlv320dac3100_fw_load()
1704 ret = regmap_write(aic31xx->regmap, AIC31XX_REG(9, reg), *data); in tlv320dac3100_fw_load()
1706 dev_err(aic31xx->dev, in tlv320dac3100_fw_load()
1713 dev_info(aic31xx->dev, "done loading DAC filter coefficients\n"); in tlv320dac3100_fw_load()
1724 ret = request_firmware(&fw, fw_name, aic31xx->dev); in tlv320dac3100_load_coeffs()
1728 ret = tlv320dac3100_fw_load(aic31xx, fw->data, fw->size); in tlv320dac3100_load_coeffs()
1741 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); in aic31xx_i2c_probe()
1743 return -ENOMEM; in aic31xx_i2c_probe()
1745 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); in aic31xx_i2c_probe()
1746 if (IS_ERR(aic31xx->regmap)) { in aic31xx_i2c_probe()
1747 ret = PTR_ERR(aic31xx->regmap); in aic31xx_i2c_probe()
1748 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in aic31xx_i2c_probe()
1752 regcache_cache_only(aic31xx->regmap, true); in aic31xx_i2c_probe()
1754 aic31xx->dev = &i2c->dev; in aic31xx_i2c_probe()
1755 aic31xx->irq = i2c->irq; in aic31xx_i2c_probe()
1757 aic31xx->codec_type = (uintptr_t)i2c_get_match_data(i2c); in aic31xx_i2c_probe()
1759 dev_set_drvdata(aic31xx->dev, aic31xx); in aic31xx_i2c_probe()
1761 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", in aic31xx_i2c_probe()
1767 aic31xx->micbias_vg = micbias_value; in aic31xx_i2c_probe()
1770 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", in aic31xx_i2c_probe()
1772 aic31xx->micbias_vg = MICBIAS_2_0V; in aic31xx_i2c_probe()
1775 if (dev_get_platdata(aic31xx->dev)) { in aic31xx_i2c_probe()
1776 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); in aic31xx_i2c_probe()
1777 aic31xx->codec_type = aic31xx->pdata.codec_type; in aic31xx_i2c_probe()
1778 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; in aic31xx_i2c_probe()
1781 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", in aic31xx_i2c_probe()
1783 if (IS_ERR(aic31xx->gpio_reset)) in aic31xx_i2c_probe()
1784 return dev_err_probe(aic31xx->dev, PTR_ERR(aic31xx->gpio_reset), in aic31xx_i2c_probe()
1787 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) in aic31xx_i2c_probe()
1788 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; in aic31xx_i2c_probe()
1790 ret = devm_regulator_bulk_get(aic31xx->dev, in aic31xx_i2c_probe()
1791 ARRAY_SIZE(aic31xx->supplies), in aic31xx_i2c_probe()
1792 aic31xx->supplies); in aic31xx_i2c_probe()
1794 return dev_err_probe(aic31xx->dev, ret, "Failed to request supplies\n"); in aic31xx_i2c_probe()
1798 if (aic31xx->irq > 0) { in aic31xx_i2c_probe()
1799 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1, in aic31xx_i2c_probe()
1804 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, in aic31xx_i2c_probe()
1810 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, in aic31xx_i2c_probe()
1812 IRQF_ONESHOT, "aic31xx-irq", in aic31xx_i2c_probe()
1815 dev_err(aic31xx->dev, "Unable to request IRQ\n"); in aic31xx_i2c_probe()
1820 if (aic31xx->codec_type == DAC3100) { in aic31xx_i2c_probe()
1821 ret = tlv320dac3100_load_coeffs(aic31xx, "tlv320dac3100-coeffs.bin"); in aic31xx_i2c_probe()
1823 dev_warn(aic31xx->dev, "Did not load any filter coefficients\n"); in aic31xx_i2c_probe()
1826 if (aic31xx->codec_type & DAC31XX_BIT) in aic31xx_i2c_probe()
1827 return devm_snd_soc_register_component(&i2c->dev, in aic31xx_i2c_probe()
1832 return devm_snd_soc_register_component(&i2c->dev, in aic31xx_i2c_probe()
1840 .name = "tlv320aic31xx-codec",