1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
43 	SOC_DAPM_ENUM("Port B source select", portb_out_src_enum);
46 static const char * const dit_mux_text[] = {"Port A", "Port B", "DIR", "SRC"};
52 static const char * const src_in_text[] = {"Port A", "Port B", "DIR"};
75 	SND_SOC_DAPM_MUX("Port B source",
93 	SND_SOC_DAPM_AIF_IN("AIF_B_RX", "Playback B", 0,
95 	SND_SOC_DAPM_AIF_OUT("AIF_B_TX", "Capture B", 0,
118 	{"Port B source", "loopback", "loopback_B"},
119 	{"Port B source", "other_port", "other_port_B"},
120 	{"Port B source", "DIR", "DIR_B"},
121 	{"Port B source", "SRC", "SRC_B"},
124 	{"DIT Out Src", "Port B", "Capture B"},
130 	{"SRC source", "Port B", "Port_B"},
156 	struct snd_soc_component *component = dai->component;  in src4xxx_set_dai_fmt()
158 	unsigned int ctrl;  in src4xxx_set_dai_fmt()  local
162 		ctrl = SRC4XXX_BUS_MASTER;  in src4xxx_set_dai_fmt()
163 		src4xxx->master[dai->id] = true;  in src4xxx_set_dai_fmt()
166 		ctrl = 0;  in src4xxx_set_dai_fmt()
167 		src4xxx->master[dai->id] = false;  in src4xxx_set_dai_fmt()
170 		return -EINVAL;  in src4xxx_set_dai_fmt()
176 		ctrl |= SRC4XXX_BUS_I2S;  in src4xxx_set_dai_fmt()
179 		ctrl |= SRC4XXX_BUS_LEFT_J;  in src4xxx_set_dai_fmt()
182 		ctrl |= SRC4XXX_BUS_RIGHT_J_24;  in src4xxx_set_dai_fmt()
185 		return -EINVAL;  in src4xxx_set_dai_fmt()
193 		return -EINVAL;  in src4xxx_set_dai_fmt()
197 	regmap_update_bits(src4xxx->regmap, SRC4XXX_BUS_FMT(dai->id),  in src4xxx_set_dai_fmt()
198 		SRC4XXX_BUS_FMT_MS_MASK, ctrl);  in src4xxx_set_dai_fmt()
206 	struct snd_soc_component *component = codec_dai->component;  in src4xxx_set_mclk_hz()
209 	dev_info(component->dev, "changing mclk rate from %d to %d Hz\n",  in src4xxx_set_mclk_hz()
210 		src4xxx->mclk_hz, freq);  in src4xxx_set_mclk_hz()
211 	src4xxx->mclk_hz = freq;  in src4xxx_set_mclk_hz()
220 	struct snd_soc_component *component = dai->component;  in src4xxx_hw_params()
227 	switch (dai->id) {  in src4xxx_hw_params()
236 	if (src4xxx->master[dai->id]) {  in src4xxx_hw_params()
237 		mclk_div = src4xxx->mclk_hz/params_rate(params);  in src4xxx_hw_params()
238 		if (src4xxx->mclk_hz != mclk_div*params_rate(params)) {  in src4xxx_hw_params()
239 			dev_err(component->dev,  in src4xxx_hw_params()
241 				src4xxx->mclk_hz, params_rate(params));  in src4xxx_hw_params()
242 			return -EINVAL;  in src4xxx_hw_params()
245 		val = ((int)mclk_div - 128) / 128;  in src4xxx_hw_params()
247 			dev_err(component->dev,  in src4xxx_hw_params()
250 			dev_err(component->dev,  in src4xxx_hw_params()
252 				params_rate(params), src4xxx->mclk_hz);  in src4xxx_hw_params()
253 			return -EINVAL;  in src4xxx_hw_params()
257 		ret = regmap_update_bits(src4xxx->regmap,  in src4xxx_hw_params()
261 			dev_err(component->dev,  in src4xxx_hw_params()
269 		switch (src4xxx->mclk_hz) {  in src4xxx_hw_params()
284 			 * -Wsometimes-uninitialized from clang.  in src4xxx_hw_params()
286 			dev_info(component->dev,  in src4xxx_hw_params()
293 		ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj);  in src4xxx_hw_params()
295 			dev_err(component->dev,  in src4xxx_hw_params()
298 		ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd);  in src4xxx_hw_params()
300 			dev_err(component->dev,  in src4xxx_hw_params()
303 		ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d);  in src4xxx_hw_params()
305 			dev_err(component->dev,  in src4xxx_hw_params()
309 		ret = regmap_update_bits(src4xxx->regmap,  in src4xxx_hw_params()
313 			dev_err(component->dev,  in src4xxx_hw_params()
320 		return regmap_update_bits(src4xxx->regmap, reg,  in src4xxx_hw_params()
323 		dev_info(dai->dev, "not setting up MCLK as not master\n");  in src4xxx_hw_params()
345 		.name = "src4xxx-portA",
364 		.name = "src4xxx-portB",
366 			.stream_name = "Playback B",
373 			.stream_name = "Capture B",
426 		return -ENOMEM;  in src4xxx_probe()
428 	src4xxx->regmap = regmap;  in src4xxx_probe()
429 	src4xxx->dev = dev;  in src4xxx_probe()
430 	src4xxx->mclk_hz = 0; /* mclk has not been configured yet */  in src4xxx_probe()
442 	ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_PWR_RST_01,  in src4xxx_probe()
445 		dev_err(dev, "Failed to port A and B : %d\n", ret);  in src4xxx_probe()
448 	ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0D,  in src4xxx_probe()
455 	ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0E,  in src4xxx_probe()