Lines Matching +full:dmic +full:- +full:sample +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
25 #include <sound/soc-dapm.h>
38 "LDO1-IN",
60 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
751 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
752 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
819 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
820 if (!rt5682->is_sdw) in rt5682_reset()
821 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
826 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
833 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
849 return -EINVAL; in rt5682_sel_asrc_clk_src()
875 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); in rt5682_button_detect()
896 if (rt5682->is_sdw) in rt5682_enable_push_button_irq()
920 * rt5682_headset_detect - Detect headset.
931 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_headset_detect()
968 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_headset_detect()
974 rt5682->jack_type = SND_JACK_HEADPHONE; in rt5682_headset_detect()
1007 rt5682->jack_type = 0; in rt5682_headset_detect()
1010 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); in rt5682_headset_detect()
1011 return rt5682->jack_type; in rt5682_headset_detect()
1019 rt5682->hs_jack = hs_jack; in rt5682_set_jack_detect()
1021 if (rt5682->is_sdw && !rt5682->first_hw_init) in rt5682_set_jack_detect()
1025 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1027 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1029 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_set_jack_detect()
1034 if (!rt5682->is_sdw) { in rt5682_set_jack_detect()
1035 switch (rt5682->pdata.jd_src) { in rt5682_set_jack_detect()
1050 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, in rt5682_set_jack_detect()
1052 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1056 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, in rt5682_set_jack_detect()
1058 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1061 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, in rt5682_set_jack_detect()
1062 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1063 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1064 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, in rt5682_set_jack_detect()
1065 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1066 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1067 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, in rt5682_set_jack_detect()
1068 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1069 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1070 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, in rt5682_set_jack_detect()
1071 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1072 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1074 &rt5682->jack_detect_work, in rt5682_set_jack_detect()
1079 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1081 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1086 dev_warn(component->dev, "Wrong JD source\n"); in rt5682_set_jack_detect()
1101 if (!rt5682->component || in rt5682_jack_detect_handler()
1102 !snd_soc_card_is_instantiated(rt5682->component->card)) { in rt5682_jack_detect_handler()
1105 &rt5682->jack_detect_work, msecs_to_jiffies(15)); in rt5682_jack_detect_handler()
1109 if (rt5682->is_sdw) { in rt5682_jack_detect_handler()
1110 if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) { in rt5682_jack_detect_handler()
1111 dev_dbg(&rt5682->slave->dev, in rt5682_jack_detect_handler()
1118 dapm = snd_soc_component_get_dapm(rt5682->component); in rt5682_jack_detect_handler()
1121 mutex_lock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1123 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) in rt5682_jack_detect_handler()
1127 if (rt5682->jack_type == 0) { in rt5682_jack_detect_handler()
1129 rt5682->jack_type = in rt5682_jack_detect_handler()
1130 rt5682_headset_detect(rt5682->component, 1); in rt5682_jack_detect_handler()
1131 rt5682->irq_work_delay_time = 0; in rt5682_jack_detect_handler()
1132 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == in rt5682_jack_detect_handler()
1135 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_jack_detect_handler()
1136 btn_type = rt5682_button_detect(rt5682->component); in rt5682_jack_detect_handler()
1148 rt5682->jack_type |= SND_JACK_BTN_0; in rt5682_jack_detect_handler()
1153 rt5682->jack_type |= SND_JACK_BTN_1; in rt5682_jack_detect_handler()
1158 rt5682->jack_type |= SND_JACK_BTN_2; in rt5682_jack_detect_handler()
1163 rt5682->jack_type |= SND_JACK_BTN_3; in rt5682_jack_detect_handler()
1168 dev_err(rt5682->component->dev, in rt5682_jack_detect_handler()
1176 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); in rt5682_jack_detect_handler()
1177 rt5682->irq_work_delay_time = 50; in rt5682_jack_detect_handler()
1180 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1183 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, in rt5682_jack_detect_handler()
1188 if (!rt5682->is_sdw) { in rt5682_jack_detect_handler()
1189 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5682_jack_detect_handler()
1191 schedule_delayed_work(&rt5682->jd_check_work, 0); in rt5682_jack_detect_handler()
1193 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_jack_detect_handler()
1224 if (rt5682->sysclk < target) { in rt5682_div_sel()
1225 dev_err(rt5682->component->dev, in rt5682_div_sel()
1226 "sysclk rate %d is too low\n", rt5682->sysclk); in rt5682_div_sel()
1230 for (i = 0; i < size - 1; i++) { in rt5682_div_sel()
1231 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); in rt5682_div_sel()
1232 if (target * div[i] == rt5682->sysclk) in rt5682_div_sel()
1234 if (target * div[i + 1] > rt5682->sysclk) { in rt5682_div_sel()
1235 dev_dbg(rt5682->component->dev, in rt5682_div_sel()
1237 rt5682->sysclk); in rt5682_div_sel()
1242 if (target * div[i] < rt5682->sysclk) in rt5682_div_sel()
1243 dev_err(rt5682->component->dev, in rt5682_div_sel()
1244 "sysclk rate %d is too high\n", rt5682->sysclk); in rt5682_div_sel()
1246 return size - 1; in rt5682_div_sel()
1250 * set_dmic_clk - Set parameter of dmic.
1256 * Choose dmic clock between 1MHz and 3MHz.
1263 snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1268 if (rt5682->pdata.dmic_clk_rate) in set_dmic_clk()
1269 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; in set_dmic_clk()
1283 snd_soc_dapm_to_component(w->dapm); in set_filter_clk()
1289 if (rt5682->is_sdw) in set_filter_clk()
1294 if (w->shift == RT5682_PWR_ADC_S1F_BIT && in set_filter_clk()
1296 ref = 256 * rt5682->lrck[RT5682_AIF2]; in set_filter_clk()
1298 ref = 256 * rt5682->lrck[RT5682_AIF1]; in set_filter_clk()
1302 if (w->shift == RT5682_PWR_ADC_S1F_BIT) in set_filter_clk()
1310 /* select over sample rate */ in set_filter_clk()
1312 if (rt5682->sysclk <= 12288000 * div_o[idx]) in set_filter_clk()
1328 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll1()
1343 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll2()
1358 snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1360 switch (w->shift) { in is_using_asrc()
1433 /* MX-26 [13] [5] */
1453 /* MX-26 [11:10] [3:2] */
1473 /* MX-26 [12] [4] */
1475 "DAC MIX", "DMIC"
1492 /* MX-79 [6:4] I2S1 ADC data location */
1512 /* MX-2B [4], MX-2B [0]*/
1543 snd_soc_dapm_to_component(w->dapm); in rt5682_hp_event()
1582 snd_soc_dapm_to_component(w->dapm); in set_dmic_power()
1586 if (rt5682->pdata.dmic_delay) in set_dmic_power()
1587 delay = rt5682->pdata.dmic_delay; in set_dmic_power()
1604 if (!rt5682->jack_type) { in set_dmic_power()
1605 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) in set_dmic_power()
1608 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) in set_dmic_power()
1622 snd_soc_dapm_to_component(w->dapm); in rt5682_set_verf()
1626 switch (w->shift) { in rt5682_set_verf()
1641 switch (w->shift) { in rt5682_set_verf()
1717 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1727 SND_SOC_DAPM_INPUT("DMIC L1"),
1728 SND_SOC_DAPM_INPUT("DMIC R1"),
1732 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1930 {"DMIC L1", NULL, "DMIC CLK"},
1931 {"DMIC L1", NULL, "DMIC1 Power"},
1932 {"DMIC R1", NULL, "DMIC CLK"},
1933 {"DMIC R1", NULL, "DMIC1 Power"},
1934 {"DMIC CLK", NULL, "DMIC ASRC"},
1943 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1948 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
2066 struct snd_soc_component *component = dai->component; in rt5682_set_tdm_slot()
2092 return -EINVAL; in rt5682_set_tdm_slot()
2101 return -EINVAL; in rt5682_set_tdm_slot()
2121 return -EINVAL; in rt5682_set_tdm_slot()
2135 struct snd_soc_component *component = dai->component; in rt5682_hw_params()
2140 rt5682->lrck[dai->id] = params_rate(params); in rt5682_hw_params()
2141 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); in rt5682_hw_params()
2145 dev_err(component->dev, "Unsupported frame size: %d\n", in rt5682_hw_params()
2147 return -EINVAL; in rt5682_hw_params()
2150 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5682_hw_params()
2151 rt5682->lrck[dai->id], pre_div, dai->id); in rt5682_hw_params()
2173 return -EINVAL; in rt5682_hw_params()
2176 switch (dai->id) { in rt5682_hw_params()
2180 if (rt5682->master[RT5682_AIF1]) { in rt5682_hw_params()
2185 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_hw_params()
2199 if (rt5682->master[RT5682_AIF2]) { in rt5682_hw_params()
2214 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_hw_params()
2215 return -EINVAL; in rt5682_hw_params()
2223 struct snd_soc_component *component = dai->component; in rt5682_set_dai_fmt()
2229 rt5682->master[dai->id] = 1; in rt5682_set_dai_fmt()
2232 rt5682->master[dai->id] = 0; in rt5682_set_dai_fmt()
2235 return -EINVAL; in rt5682_set_dai_fmt()
2246 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2249 return -EINVAL; in rt5682_set_dai_fmt()
2252 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2256 return -EINVAL; in rt5682_set_dai_fmt()
2259 return -EINVAL; in rt5682_set_dai_fmt()
2278 return -EINVAL; in rt5682_set_dai_fmt()
2281 switch (dai->id) { in rt5682_set_dai_fmt()
2289 tdm_ctrl | rt5682->master[dai->id]); in rt5682_set_dai_fmt()
2292 if (rt5682->master[dai->id] == 0) in rt5682_set_dai_fmt()
2299 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_set_dai_fmt()
2300 return -EINVAL; in rt5682_set_dai_fmt()
2311 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) in rt5682_set_component_sysclk()
2332 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5682_set_component_sysclk()
2333 return -EINVAL; in rt5682_set_component_sysclk()
2338 if (rt5682->master[RT5682_AIF2]) { in rt5682_set_component_sysclk()
2344 rt5682->sysclk = freq; in rt5682_set_component_sysclk()
2345 rt5682->sysclk_src = clk_id; in rt5682_set_component_sysclk()
2347 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5682_set_component_sysclk()
2362 if (source == rt5682->pll_src[pll_id] && in rt5682_set_component_pll()
2363 freq_in == rt5682->pll_in[pll_id] && in rt5682_set_component_pll()
2364 freq_out == rt5682->pll_out[pll_id]) in rt5682_set_component_pll()
2368 dev_dbg(component->dev, "PLL disabled\n"); in rt5682_set_component_pll()
2370 rt5682->pll_in[pll_id] = 0; in rt5682_set_component_pll()
2371 rt5682->pll_out[pll_id] = 0; in rt5682_set_component_pll()
2385 dev_err(component->dev, "Unknown PLL2 Source %d\n", in rt5682_set_component_pll()
2387 return -EINVAL; in rt5682_set_component_pll()
2397 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2401 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2409 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2413 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2453 dev_err(component->dev, "Unknown PLL1 Source %d\n", in rt5682_set_component_pll()
2455 return -EINVAL; in rt5682_set_component_pll()
2460 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2465 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2476 rt5682->pll_in[pll_id] = freq_in; in rt5682_set_component_pll()
2477 rt5682->pll_out[pll_id] = freq_out; in rt5682_set_component_pll()
2478 rt5682->pll_src[pll_id] = source; in rt5682_set_component_pll()
2485 struct snd_soc_component *component = dai->component; in rt5682_set_bclk1_ratio()
2488 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk1_ratio()
2508 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); in rt5682_set_bclk1_ratio()
2509 return -EINVAL; in rt5682_set_bclk1_ratio()
2517 struct snd_soc_component *component = dai->component; in rt5682_set_bclk2_ratio()
2520 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk2_ratio()
2534 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); in rt5682_set_bclk2_ratio()
2535 return -EINVAL; in rt5682_set_bclk2_ratio()
2548 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2550 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2556 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2560 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2562 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2579 if (!rt5682->master[RT5682_AIF1]) { in rt5682_clk_check()
2580 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); in rt5682_clk_check()
2595 return -EINVAL; in rt5682_wclk_prepare()
2597 component = rt5682->component; in rt5682_wclk_prepare()
2635 component = rt5682->component; in rt5682_wclk_unprepare()
2642 if (!rt5682->jack_type) in rt5682_wclk_unprepare()
2666 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682_wclk_recalc_rate()
2668 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && in rt5682_wclk_recalc_rate()
2669 rt5682->lrck[RT5682_AIF1] != CLK_44) { in rt5682_wclk_recalc_rate()
2670 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_recalc_rate()
2675 return rt5682->lrck[RT5682_AIF1]; in rt5682_wclk_recalc_rate()
2678 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, in rt5682_wclk_round_rate() argument
2687 return -EINVAL; in rt5682_wclk_round_rate()
2689 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682_wclk_round_rate()
2692 if (rate != CLK_48 && rate != CLK_44) { in rt5682_wclk_round_rate()
2693 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_round_rate()
2695 rate = CLK_48; in rt5682_wclk_round_rate()
2698 return rate; in rt5682_wclk_round_rate()
2701 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, in rt5682_wclk_set_rate() argument
2714 return -EINVAL; in rt5682_wclk_set_rate()
2716 component = rt5682->component; in rt5682_wclk_set_rate()
2720 * it is fixed or set to 48MHz before setting wclk rate. It's a in rt5682_wclk_set_rate()
2727 dev_warn(rt5682->i2c_dev, in rt5682_wclk_set_rate()
2732 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", in rt5682_wclk_set_rate()
2736 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, in rt5682_wclk_set_rate()
2739 clk_pll2_out = rate * 512; in rt5682_wclk_set_rate()
2746 rt5682->lrck[RT5682_AIF1] = rate; in rt5682_wclk_set_rate()
2748 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); in rt5682_wclk_set_rate()
2753 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_wclk_set_rate()
2766 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); in rt5682_bclk_recalc_rate()
2782 static unsigned long rt5682_bclk_get_factor(unsigned long rate, in rt5682_bclk_get_factor() argument
2787 factor = rate / parent_rate; in rt5682_bclk_get_factor()
2798 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, in rt5682_bclk_round_rate() argument
2807 return -EINVAL; in rt5682_bclk_round_rate()
2812 * some rounding down based on the parent WCLK rate in rt5682_bclk_round_rate()
2816 factor = rt5682_bclk_get_factor(rate, *parent_rate); in rt5682_bclk_round_rate()
2821 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, in rt5682_bclk_set_rate() argument
2832 return -EINVAL; in rt5682_bclk_set_rate()
2834 component = rt5682->component; in rt5682_bclk_set_rate()
2836 factor = rt5682_bclk_get_factor(rate, parent_rate); in rt5682_bclk_set_rate()
2839 if (dai->id == RT5682_AIF1) in rt5682_bclk_set_rate()
2842 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", in rt5682_bclk_set_rate()
2844 return -ENODEV; in rt5682_bclk_set_rate()
2864 struct device *dev = rt5682->i2c_dev; in rt5682_register_dai_clks()
2865 struct rt5682_platform_data *pdata = &rt5682->pdata; in rt5682_register_dai_clks()
2873 dai_clk_hw = &rt5682->dai_clks_hw[i]; in rt5682_register_dai_clks()
2878 if (rt5682->mclk) { in rt5682_register_dai_clks()
2879 parent = __clk_get_hw(rt5682->mclk); in rt5682_register_dai_clks()
2886 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]; in rt5682_register_dai_clks()
2892 return -EINVAL; in rt5682_register_dai_clks()
2895 init.name = pdata->dai_clk_names[i]; in rt5682_register_dai_clks()
2898 dai_clk_hw->init = &init; in rt5682_register_dai_clks()
2907 if (dev->of_node) { in rt5682_register_dai_clks()
2931 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_probe()
2933 rt5682->component = component; in rt5682_probe()
2935 if (rt5682->is_sdw) { in rt5682_probe()
2936 slave = rt5682->slave; in rt5682_probe()
2938 &slave->initialization_complete, in rt5682_probe()
2941 dev_err(&slave->dev, "Initialization not complete, timed out\n"); in rt5682_probe()
2942 return -ETIMEDOUT; in rt5682_probe()
2965 if (rt5682->is_sdw) in rt5682_suspend()
2968 if (rt5682->irq) in rt5682_suspend()
2969 disable_irq(rt5682->irq); in rt5682_suspend()
2971 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_suspend()
2972 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_suspend()
2973 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { in rt5682_suspend()
3008 regcache_cache_only(rt5682->regmap, true); in rt5682_suspend()
3009 regcache_mark_dirty(rt5682->regmap); in rt5682_suspend()
3017 if (rt5682->is_sdw) in rt5682_resume()
3020 regcache_cache_only(rt5682->regmap, false); in rt5682_resume()
3021 regcache_sync(rt5682->regmap); in rt5682_resume()
3023 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { in rt5682_resume()
3035 rt5682->jack_type = 0; in rt5682_resume()
3037 &rt5682->jack_detect_work, msecs_to_jiffies(0)); in rt5682_resume()
3039 if (rt5682->irq) in rt5682_resume()
3040 enable_irq(rt5682->irq); in rt5682_resume()
3087 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5682_parse_dt()
3088 &rt5682->pdata.dmic1_data_pin); in rt5682_parse_dt()
3089 device_property_read_u32(dev, "realtek,dmic1-clk-pin", in rt5682_parse_dt()
3090 &rt5682->pdata.dmic1_clk_pin); in rt5682_parse_dt()
3091 device_property_read_u32(dev, "realtek,jd-src", in rt5682_parse_dt()
3092 &rt5682->pdata.jd_src); in rt5682_parse_dt()
3093 device_property_read_u32(dev, "realtek,btndet-delay", in rt5682_parse_dt()
3094 &rt5682->pdata.btndet_delay); in rt5682_parse_dt()
3095 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", in rt5682_parse_dt()
3096 &rt5682->pdata.dmic_clk_rate); in rt5682_parse_dt()
3097 device_property_read_u32(dev, "realtek,dmic-delay-ms", in rt5682_parse_dt()
3098 &rt5682->pdata.dmic_delay); in rt5682_parse_dt()
3100 if (device_property_read_string_array(dev, "clock-output-names", in rt5682_parse_dt()
3101 rt5682->pdata.dai_clk_names, in rt5682_parse_dt()
3104 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], in rt5682_parse_dt()
3105 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); in rt5682_parse_dt()
3107 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, in rt5682_parse_dt()
3108 "realtek,dmic-clk-driving-high"); in rt5682_parse_dt()
3116 rt5682->ldo1_en = devm_gpiod_get_optional(dev, in rt5682_get_ldo1()
3117 "realtek,ldo1-en", in rt5682_get_ldo1()
3119 if (IS_ERR(rt5682->ldo1_en)) { in rt5682_get_ldo1()
3121 return PTR_ERR(rt5682->ldo1_en); in rt5682_get_ldo1()
3132 mutex_lock(&rt5682->calibrate_mutex); in rt5682_calibrate()
3135 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); in rt5682_calibrate()
3136 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); in rt5682_calibrate()
3138 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); in rt5682_calibrate()
3139 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); in rt5682_calibrate()
3140 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); in rt5682_calibrate()
3141 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); in rt5682_calibrate()
3142 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); in rt5682_calibrate()
3143 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); in rt5682_calibrate()
3144 if (rt5682->ve_ic) in rt5682_calibrate()
3145 regmap_write(rt5682->regmap, RT5682_CHOP_ADC, 0x7005); in rt5682_calibrate()
3147 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); in rt5682_calibrate()
3148 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); in rt5682_calibrate()
3149 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); in rt5682_calibrate()
3150 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); in rt5682_calibrate()
3151 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); in rt5682_calibrate()
3152 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3153 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); in rt5682_calibrate()
3154 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); in rt5682_calibrate()
3155 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3157 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); in rt5682_calibrate()
3160 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); in rt5682_calibrate()
3168 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); in rt5682_calibrate()
3171 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); in rt5682_calibrate()
3172 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); in rt5682_calibrate()
3173 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); in rt5682_calibrate()
3174 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); in rt5682_calibrate()
3175 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); in rt5682_calibrate()
3176 if (rt5682->ve_ic) in rt5682_calibrate()
3177 regmap_write(rt5682->regmap, RT5682_CHOP_ADC, 0x2005); in rt5682_calibrate()
3179 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); in rt5682_calibrate()
3180 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); in rt5682_calibrate()
3181 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); in rt5682_calibrate()
3183 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_calibrate()