Lines Matching +full:12 +full:- +full:13
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
17 /* I/O - Output */
20 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
34 /* Mixer - D-D */
47 /* Mixer - PDM */
56 /* Mixer - ADC */
61 /* Mixer - DAC */
77 /* Format - ADC/DAC */
86 /* Format - TDM Control */
91 /* Function - Analog */
121 /* Function - Digital */
229 #define RT5670_CBJ_BST1_MASK (0xf << 12)
230 #define RT5670_CBJ_BST1_SFT (12)
236 #define RT5670_CBJ_MN_JD (0x1 << 12)
241 #define RT5670_BST_MASK1 (0xf<<12)
242 #define RT5670_BST_SFT1 12
287 #define RT5670_M_DAC_L2_VOL (0x1 << 13)
288 #define RT5670_M_DAC_L2_VOL_SFT 13
289 #define RT5670_M_DAC_R2_VOL (0x1 << 12)
290 #define RT5670_M_DAC_R2_VOL_SFT 12
311 #define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
312 #define RT5670_STO1_ADC_R_BST_SFT 12
329 #define RT5670_M_ADC_L2 (0x1 << 13)
330 #define RT5670_M_ADC_L2_SFT 13
331 #define RT5670_ADC_1_SRC_MASK (0x1 << 12)
332 #define RT5670_ADC_1_SRC_SFT 12
333 #define RT5670_ADC_1_SRC_ADC (0x1 << 12)
334 #define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
351 #define RT5670_M_MONO_ADC_L2 (0x1 << 13)
352 #define RT5670_M_MONO_ADC_L2_SFT 13
353 #define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
354 #define RT5670_MONO_ADC_L1_SRC_SFT 12
355 #define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
356 #define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
401 #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
402 #define RT5670_DAC_L1_STO_L_VOL_SFT 13
403 #define RT5670_M_DAC_L2 (0x1 << 12)
404 #define RT5670_M_DAC_L2_SFT 12
427 #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
428 #define RT5670_DAC_L1_MONO_L_VOL_SFT 13
429 #define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
430 #define RT5670_M_DAC_L2_MONO_L_SFT 12
455 #define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
456 #define RT5670_M_DAC_L2_DAC_L_SFT 13
457 #define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
458 #define RT5670_DAC_L2_DAC_L_VOL_SFT 12
477 #define RT5670_RXDP_SEL_MASK (0x7 << 13)
478 #define RT5670_RXDP_SEL_SFT 13
505 #define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
506 #define RT5670_IF2_ADC_IN_SFT 12
521 #define RT5670_PDM1_R_MASK (0x1 << 13)
522 #define RT5670_PDM1_R_SFT 13
523 #define RT5670_M_PDM1_R (0x1 << 12)
524 #define RT5670_M_PDM1_R_SFT 12
540 #define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
541 #define RT5670_G_HP_L_RM_L_SFT 13
552 #define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
553 #define RT5670_G_BST1_RM_L_SFT 13
562 #define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
563 #define RT5670_G_HP_R_RM_R_SFT 13
574 #define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
575 #define RT5670_G_BST1_RM_R_SFT 13
588 #define RT5670_M_DAC1_HM (0x1 << 13)
589 #define RT5670_M_DAC1_HM_SFT 13
590 #define RT5670_G_HPOMIX_MASK (0x1 << 12)
591 #define RT5670_G_HPOMIX_SFT 12
606 #define RT5670_M_OV_R_MM (0x1 << 13)
607 #define RT5670_M_OV_R_MM_SFT 13
608 #define RT5670_M_OV_L_MM (0x1 << 12)
609 #define RT5670_M_OV_L_MM_SFT 12
620 #define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
621 #define RT5670_G_BST3_OM_L_SFT 13
632 #define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
633 #define RT5670_G_DAC_R2_OM_L_SFT 13
650 #define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
651 #define RT5670_G_BST4_OM_R_SFT 13
662 #define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
663 #define RT5670_G_DAC_L2_OM_R_SFT 13
684 #define RT5670_M_OV_L_LM (0x1 << 13)
685 #define RT5670_M_OV_L_LM_SFT 13
686 #define RT5670_M_OV_R_LM (0x1 << 12)
687 #define RT5670_M_OV_R_LM_SFT 12
696 #define RT5670_PWR_DAC_L1 (0x1 << 12)
697 #define RT5670_PWR_DAC_L1_BIT 12
716 #define RT5670_PWR_ADC_MF_R (0x1 << 13)
717 #define RT5670_PWR_ADC_MF_R_BIT 13
718 #define RT5670_PWR_I2S_DSP (0x1 << 12)
719 #define RT5670_PWR_I2S_DSP_BIT 12
738 #define RT5670_PWR_MB (0x1 << 13)
739 #define RT5670_PWR_MB_BIT 13
740 #define RT5670_PWR_LM (0x1 << 12)
741 #define RT5670_PWR_LM_BIT 12
760 #define RT5670_PWR_BST2 (0x1 << 13)
761 #define RT5670_PWR_BST2_BIT 13
804 #define RT5670_I2S_IF_MASK (0x7 << 12)
805 #define RT5670_I2S_IF_SFT 12
844 #define RT5670_I2S_PD1_MASK (0x7 << 12)
845 #define RT5670_I2S_PD1_SFT 12
846 #define RT5670_I2S_PD1_1 (0x0 << 12)
847 #define RT5670_I2S_PD1_2 (0x1 << 12)
848 #define RT5670_I2S_PD1_3 (0x2 << 12)
849 #define RT5670_I2S_PD1_4 (0x3 << 12)
850 #define RT5670_I2S_PD1_6 (0x4 << 12)
851 #define RT5670_I2S_PD1_8 (0x5 << 12)
852 #define RT5670_I2S_PD1_12 (0x6 << 12)
853 #define RT5670_I2S_PD1_16 (0x7 << 12)
902 #define RT5670_ADC_R_OSR_MASK (0x3 << 12)
903 #define RT5670_ADC_R_OSR_SFT 12
904 #define RT5670_ADC_R_OSR_128 (0x0 << 12)
905 #define RT5670_ADC_R_OSR_64 (0x1 << 12)
906 #define RT5670_ADC_R_OSR_32 (0x2 << 12)
907 #define RT5670_ADC_R_OSR_16 (0x3 << 12)
922 #define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
923 #define RT5670_DMIC_1L_LH_SFT 13
924 #define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
925 #define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
926 #define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
927 #define RT5670_DMIC_1R_LH_SFT 12
928 #define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
929 #define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
990 #define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12)
991 #define RT5670_PLL_M_SFT 12
1004 #define RT5670_I2S2_F_MASK (0x1 << 12)
1005 #define RT5670_I2S2_F_SFT 12
1006 #define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
1007 #define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1026 #define RT5670_DA_STO_CLK_SEL_MASK (0xf << 12)
1027 #define RT5670_DA_STO_CLK_SEL_SFT 12
1036 #define RT5670_UP_CLK_SEL_MASK (0xf << 12)
1037 #define RT5670_UP_CLK_SEL_SFT 12
1046 #define RT5670_I2S1_PD_MASK (0x7 << 12)
1047 #define RT5670_I2S1_PD_SFT 12
1076 #define RT5670_CLSD_RATIO_MASK (0xf << 12)
1077 #define RT5670_CLSD_RATIO_SFT 12
1134 #define RT5670_DEPOP_MASK (0x1 << 13)
1135 #define RT5670_DEPOP_SFT 13
1136 #define RT5670_DEPOP_AUTO (0x0 << 13)
1137 #define RT5670_DEPOP_MAN (0x1 << 13)
1138 #define RT5670_RAMP_MASK (0x1 << 12)
1139 #define RT5670_RAMP_SFT 12
1140 #define RT5670_RAMP_DIS (0x0 << 12)
1141 #define RT5670_RAMP_EN (0x1 << 12)
1168 #define RT5670_CP_SYS_MASK (0x7 << 12)
1169 #define RT5670_CP_SYS_SFT 12
1225 #define RT5670_MIC1_CLK_MASK (0x1 << 13)
1226 #define RT5670_MIC1_CLK_SFT 13
1227 #define RT5670_MIC1_CLK_DIS (0x0 << 13)
1228 #define RT5670_MIC1_CLK_EN (0x1 << 13)
1229 #define RT5670_MIC2_CLK_MASK (0x1 << 12)
1230 #define RT5670_MIC2_CLK_SFT 12
1231 #define RT5670_MIC2_CLK_DIS (0x0 << 12)
1232 #define RT5670_MIC2_CLK_EN (0x1 << 12)
1277 #define RT5670_EQ_CD_MASK (0x1 << 13)
1278 #define RT5670_EQ_CD_SFT 13
1279 #define RT5670_EQ_CD_DIS (0x0 << 13)
1280 #define RT5670_EQ_CD_EN (0x1 << 13)
1342 #define RT5670_DRC_AGC_UPD (0x1 << 13)
1343 #define RT5670_DRC_AGC_UPD_BIT 13
1374 #define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
1375 #define RT5670_DRC_AGC_NGB_SFT 12
1390 #define RT5670_JD_MASK (0x7 << 13)
1391 #define RT5670_JD_SFT 13
1392 #define RT5670_JD_DIS (0x0 << 13)
1393 #define RT5670_JD_GPIO1 (0x1 << 13)
1394 #define RT5670_JD_JD1_IN4P (0x2 << 13)
1395 #define RT5670_JD_JD2_IN4N (0x3 << 13)
1396 #define RT5670_JD_GPIO2 (0x4 << 13)
1397 #define RT5670_JD_GPIO3 (0x5 << 13)
1398 #define RT5670_JD_GPIO4 (0x6 << 13)
1457 #define RT5670_JD_STKY_MASK (0x1 << 13)
1458 #define RT5670_JD_STKY_SFT 13
1459 #define RT5670_JD_STKY_DIS (0x0 << 13)
1460 #define RT5670_JD_STKY_EN (0x1 << 13)
1461 #define RT5670_OT_STKY_MASK (0x1 << 12)
1462 #define RT5670_OT_STKY_SFT 12
1463 #define RT5670_OT_STKY_DIS (0x0 << 12)
1464 #define RT5670_OT_STKY_EN (0x1 << 12)
1517 #define RT5670_GP3_PIN_MASK (0x3 << 12)
1518 #define RT5670_GP3_PIN_SFT 12
1519 #define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
1520 #define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1521 #define RT5670_GP3_PIN_IRQ (0x2 << 12)
1634 #define RT5670_BB_CT_MASK (0x7 << 12)
1635 #define RT5670_BB_CT_SFT 12
1636 #define RT5670_BB_CT_A (0x0 << 12)
1637 #define RT5670_BB_CT_B (0x1 << 12)
1638 #define RT5670_BB_CT_C (0x2 << 12)
1639 #define RT5670_BB_CT_D (0x3 << 12)
1656 #define RT5670_M_MP3_MASK (0x1 << 13)
1657 #define RT5670_M_MP3_SFT 13
1658 #define RT5670_M_MP3_DIS (0x0 << 13)
1659 #define RT5670_M_MP3_EN (0x1 << 13)
1672 #define RT5670_MP3_WT_MASK (0x1 << 13)
1673 #define RT5670_MP3_WT_SFT 13
1674 #define RT5670_MP3_WT_1_4 (0x0 << 13)
1675 #define RT5670_MP3_WT_1_2 (0x1 << 13)
1690 #define RT5670_3D_BT_MASK (0x1 << 13)
1691 #define RT5670_3D_BT_SFT 13
1692 #define RT5670_3D_BT_DIS (0x0 << 13)
1693 #define RT5670_3D_BT_EN (0x1 << 13)
1714 #define RT5670_HPF_CF_L_MASK (0x7 << 12)
1715 #define RT5670_HPF_CF_L_SFT 12
1777 #define RT5670_OUT_SV_MASK (0x1 << 13)
1778 #define RT5670_OUT_SV_SFT 13
1779 #define RT5670_OUT_SV_DIS (0x0 << 13)
1780 #define RT5670_OUT_SV_EN (0x1 << 13)
1781 #define RT5670_HP_SV_MASK (0x1 << 12)
1782 #define RT5670_HP_SV_SFT 12
1783 #define RT5670_HP_SV_DIS (0x0 << 12)
1784 #define RT5670_HP_SV_EN (0x1 << 12)
1821 #define RT5670_3D_SPK_M_MASK (0x3 << 13)
1822 #define RT5670_3D_SPK_M_SFT 13
1855 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1856 #define RT5670_WND_WIND_SFT 13
1857 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1858 #define RT5670_WND_STRONG_SFT 12
1882 #define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
1905 #define RT5670_RST_DSP (0x1 << 13)
1906 #define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1907 #define RT5670_IF1_ADC1_IN1_SFT 12