Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
17 /* I/O - Output */
20 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
34 /* Mixer - D-D */
47 /* Mixer - PDM */
56 /* Mixer - ADC */
61 /* Mixer - DAC */
77 /* Format - ADC/DAC */
86 /* Format - TDM Control */
91 /* Function - Analog */
121 /* Function - Digital */
237 #define RT5670_CAPLESS_EN (0x1 << 11)
313 #define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
314 #define RT5670_STO1_ADC_COMP_SFT 10
335 #define RT5670_ADC_2_SRC_MASK (0x1 << 11)
336 #define RT5670_ADC_2_SRC_SFT 11
337 #define RT5670_ADC_SRC_MASK (0x1 << 10)
338 #define RT5670_ADC_SRC_SFT 10
357 #define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
358 #define RT5670_MONO_ADC_L2_SRC_SFT 11
359 #define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
360 #define RT5670_MONO_ADC_L_SRC_SFT 10
381 #define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
382 #define RT5670_DAC1_R_SEL_SFT 10
383 #define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
384 #define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
385 #define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
386 #define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
405 #define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
406 #define RT5670_DAC_L2_STO_L_VOL_SFT 11
431 #define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
432 #define RT5670_DAC_L2_MONO_L_VOL_SFT 11
433 #define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
434 #define RT5670_M_DAC_R2_MONO_L_SFT 10
459 #define RT5670_M_STO_R_DAC_R (0x1 << 11)
460 #define RT5670_M_STO_R_DAC_R_SFT 11
461 #define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
462 #define RT5670_STO_R_DAC_R_VOL_SFT 10
479 #define RT5670_RXDP_SRC_MASK (0x3 << 11)
480 #define RT5670_RXDP_SRC_SFT 11
481 #define RT5670_RXDP_SRC_NOR (0x0 << 11)
482 #define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
483 #define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
507 #define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
508 #define RT5670_IF2_DAC_SEL_SFT 10
525 #define RT5670_PDM2_L_MASK (0x1 << 11)
526 #define RT5670_PDM2_L_SFT 11
527 #define RT5670_M_PDM2_L (0x1 << 10)
528 #define RT5670_M_PDM2_L_SFT 10
542 #define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
543 #define RT5670_G_IN_L_RM_L_SFT 10
564 #define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
565 #define RT5670_G_IN_R_RM_R_SFT 10
610 #define RT5670_G_MONOMIX_MASK (0x1 << 10)
611 #define RT5670_G_MONOMIX_SFT 10
622 #define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
623 #define RT5670_G_BST2_OM_L_SFT 10
634 #define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
635 #define RT5670_G_DAC_L2_OM_L_SFT 10
652 #define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
653 #define RT5670_G_BST2_OM_R_SFT 10
664 #define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
665 #define RT5670_G_DAC_R2_OM_R_SFT 10
688 #define RT5670_G_LOUTMIX_MASK (0x1 << 11)
689 #define RT5670_G_LOUTMIX_SFT 11
698 #define RT5670_PWR_DAC_R1 (0x1 << 11)
699 #define RT5670_PWR_DAC_R1_BIT 11
720 #define RT5670_PWR_DAC_S1F (0x1 << 11)
721 #define RT5670_PWR_DAC_S1F_BIT 11
722 #define RT5670_PWR_DAC_MF_L (0x1 << 10)
723 #define RT5670_PWR_DAC_MF_L_BIT 10
742 #define RT5670_PWR_BG (0x1 << 11)
743 #define RT5670_PWR_BG_BIT 11
762 #define RT5670_PWR_MB1 (0x1 << 11)
763 #define RT5670_PWR_MB1_BIT 11
764 #define RT5670_PWR_MB2 (0x1 << 10)
765 #define RT5670_PWR_MB2_BIT 10
782 #define RT5670_PWR_RM_L (0x1 << 11)
783 #define RT5670_PWR_RM_L_BIT 11
784 #define RT5670_PWR_RM_R (0x1 << 10)
785 #define RT5670_PWR_RM_R_BIT 10
788 #define RT5670_PWR_HV_L (0x1 << 11)
789 #define RT5670_PWR_HV_L_BIT 11
790 #define RT5670_PWR_HV_R (0x1 << 10)
791 #define RT5670_PWR_HV_R_BIT 10
806 #define RT5670_I2S_O_CP_MASK (0x3 << 10)
807 #define RT5670_I2S_O_CP_SFT 10
808 #define RT5670_I2S_O_CP_OFF (0x0 << 10)
809 #define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
810 #define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
854 #define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
855 #define RT5670_I2S_BCLK_MS2_SFT 11
856 #define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
857 #define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
908 #define RT5670_DAHPF_EN (0x1 << 11)
909 #define RT5670_DAHPF_EN_SFT 11
910 #define RT5670_ADHPF_EN (0x1 << 10)
911 #define RT5670_ADHPF_EN_SFT 10
930 #define RT5670_DMIC_2_DP_MASK (0x1 << 10)
931 #define RT5670_DMIC_2_DP_SFT 10
932 #define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
933 #define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
967 #define RT5670_PLL1_SRC_MASK (0x7 << 11)
968 #define RT5670_PLL1_SRC_SFT 11
969 #define RT5670_PLL1_SRC_MCLK (0x0 << 11)
970 #define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
971 #define RT5670_PLL1_SRC_BCLK2 (0x2 << 11)
972 #define RT5670_PLL1_SRC_BCLK3 (0x3 << 11)
992 #define RT5670_PLL_M_BP (0x1 << 11)
993 #define RT5670_PLL_M_BP_SFT 11
1052 #define RT5670_HP_OVCD_MASK (0x1 << 10)
1053 #define RT5670_HP_OVCD_SFT 10
1054 #define RT5670_HP_OVCD_DIS (0x0 << 10)
1055 #define RT5670_HP_OVCD_EN (0x1 << 10)
1078 #define RT5670_CLSD_OM_MASK (0x1 << 11)
1079 #define RT5670_CLSD_OM_SFT 11
1080 #define RT5670_CLSD_OM_MONO (0x0 << 11)
1081 #define RT5670_CLSD_OM_STO (0x1 << 11)
1082 #define RT5670_CLSD_SCH_MASK (0x1 << 10)
1083 #define RT5670_CLSD_SCH_SFT 10
1084 #define RT5670_CLSD_SCH_L (0x0 << 10)
1085 #define RT5670_CLSD_SCH_S (0x1 << 10)
1142 #define RT5670_BPS_MASK (0x1 << 11)
1143 #define RT5670_BPS_SFT 11
1144 #define RT5670_BPS_DIS (0x0 << 11)
1145 #define RT5670_BPS_EN (0x1 << 11)
1146 #define RT5670_FAST_UPDN_MASK (0x1 << 10)
1147 #define RT5670_FAST_UPDN_SFT 10
1148 #define RT5670_FAST_UPDN_DIS (0x0 << 10)
1149 #define RT5670_FAST_UPDN_EN (0x1 << 10)
1186 #define RT5670_OSW_L_MASK (0x1 << 11)
1187 #define RT5670_OSW_L_SFT 11
1188 #define RT5670_OSW_L_DIS (0x0 << 11)
1189 #define RT5670_OSW_L_EN (0x1 << 11)
1190 #define RT5670_OSW_R_MASK (0x1 << 10)
1191 #define RT5670_OSW_R_SFT 10
1192 #define RT5670_OSW_R_DIS (0x0 << 10)
1193 #define RT5670_OSW_R_EN (0x1 << 10)
1233 #define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1234 #define RT5670_MIC1_OVCD_SFT 11
1235 #define RT5670_MIC1_OVCD_DIS (0x0 << 11)
1236 #define RT5670_MIC1_OVCD_EN (0x1 << 11)
1399 #define RT5670_JD_HP_MASK (0x1 << 11)
1400 #define RT5670_JD_HP_SFT 11
1401 #define RT5670_JD_HP_DIS (0x0 << 11)
1402 #define RT5670_JD_HP_EN (0x1 << 11)
1403 #define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1404 #define RT5670_JD_HP_TRG_SFT 10
1405 #define RT5670_JD_HP_TRG_LO (0x0 << 10)
1406 #define RT5670_JD_HP_TRG_HI (0x1 << 10)
1465 #define RT5670_JD_P_MASK (0x1 << 11)
1466 #define RT5670_JD_P_SFT 11
1467 #define RT5670_JD_P_NOR (0x0 << 11)
1468 #define RT5670_JD_P_INV (0x1 << 11)
1469 #define RT5670_OT_P_MASK (0x1 << 10)
1470 #define RT5670_OT_P_SFT 10
1471 #define RT5670_OT_P_NOR (0x0 << 10)
1472 #define RT5670_OT_P_INV (0x1 << 10)
1487 #define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1488 #define RT5670_MB1_OC_STKY_SFT 11
1489 #define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
1490 #define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1491 #define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1492 #define RT5670_MB2_OC_STKY_SFT 10
1493 #define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
1494 #define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1522 #define RT5670_GP4_PIN_MASK (0x1 << 11)
1523 #define RT5670_GP4_PIN_SFT 11
1524 #define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
1525 #define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1526 #define RT5670_DP_SIG_MASK (0x1 << 10)
1527 #define RT5670_DP_SIG_SFT 10
1528 #define RT5670_DP_SIG_TEST (0x0 << 10)
1529 #define RT5670_DP_SIG_AP (0x1 << 10)
1566 #define RT5670_GP4_PF_MASK (0x1 << 11)
1567 #define RT5670_GP4_PF_SFT 11
1568 #define RT5670_GP4_PF_IN (0x0 << 11)
1569 #define RT5670_GP4_PF_OUT (0x1 << 11)
1570 #define RT5670_GP4_OUT_MASK (0x1 << 10)
1571 #define RT5670_GP4_OUT_SFT 10
1572 #define RT5670_GP4_OUT_LO (0x0 << 10)
1573 #define RT5670_GP4_OUT_HI (0x1 << 10)
1694 #define RT5670_3D_1F_MIX_MASK (0x3 << 11)
1695 #define RT5670_3D_1F_MIX_SFT 11
1696 #define RT5670_3D_HP_M_MASK (0x1 << 10)
1697 #define RT5670_3D_HP_M_SFT 10
1698 #define RT5670_3D_HP_M_SUR (0x0 << 10)
1699 #define RT5670_3D_HP_M_FRO (0x1 << 10)
1716 #define RT5670_1ST_HPF_MASK (0x1 << 11)
1717 #define RT5670_1ST_HPF_SFT 11
1718 #define RT5670_1ST_HPF_DIS (0x0 << 11)
1719 #define RT5670_1ST_HPF_EN (0x1 << 11)
1732 #define RT5670_SI_DAC_MASK (0x1 << 11)
1733 #define RT5670_SI_DAC_SFT 11
1734 #define RT5670_SI_DAC_AUTO (0x0 << 11)
1735 #define RT5670_SI_DAC_TEST (0x1 << 11)
1736 #define RT5670_DC_CAL_M_MASK (0x1 << 10)
1737 #define RT5670_DC_CAL_M_SFT 10
1738 #define RT5670_DC_CAL_M_CAL (0x0 << 10)
1739 #define RT5670_DC_CAL_M_NOR (0x1 << 10)
1785 #define RT5670_ZCD_DIG_MASK (0x1 << 11)
1786 #define RT5670_ZCD_DIG_SFT 11
1787 #define RT5670_ZCD_DIG_DIS (0x0 << 11)
1788 #define RT5670_ZCD_DIG_EN (0x1 << 11)
1789 #define RT5670_ZCD_MASK (0x1 << 10)
1790 #define RT5670_ZCD_SFT 10
1791 #define RT5670_ZCD_PD (0x0 << 10)
1792 #define RT5670_ZCD_PU (0x1 << 10)
1811 #define RT5670_TDM_DATA_MODE_SEL (0x1 << 11)
1812 #define RT5670_TDM_DATA_MODE_NOR (0x0 << 11)
1813 #define RT5670_TDM_DATA_MODE_50FS (0x1 << 11)
1835 #define RT5670_WND_FC_NW_MASK (0x3f << 10)
1836 #define RT5670_WND_FC_NW_SFT 10
1855 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1857 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1868 #define RT5670_DP_SPK_MASK (0x1 << 10)
1869 #define RT5670_DP_SPK_SFT 10
1870 #define RT5670_DP_SPK_DIS (0x0 << 10)
1871 #define RT5670_DP_SPK_EN (0x1 << 10)
1908 #define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1909 #define RT5670_IF1_ADC1_IN2_SFT 11
1910 #define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1911 #define RT5670_IF1_ADC2_IN1_SFT 10