Lines Matching +full:12 +full:- +full:13
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
112 /* Format - ADC/DAC */
120 /* Format - TDM Control */
129 /* Function - Analog */
158 /* Function - Digital */
483 #define RT5665_JD_MODE (0x1 << 13)
484 #define RT5665_JD_MODE_SFT 13
517 #define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
518 #define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
519 #define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
530 #define RT5665_M_DAC2_L_VOL (0x1 << 13)
531 #define RT5665_M_DAC2_L_VOL_SFT 13
532 #define RT5665_M_DAC2_R_VOL (0x1 << 12)
533 #define RT5665_M_DAC2_R_VOL_SFT 12
558 #define RT5665_M_DAC3_L_VOL (0x1 << 13)
559 #define RT5665_M_DAC3_L_VOL_SFT 13
560 #define RT5665_M_DAC3_R_VOL (0x1 << 12)
561 #define RT5665_M_DAC3_R_VOL_SFT 12
582 #define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
583 #define RT5665_STO1_ADC_R_BST_SFT 12
588 #define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
589 #define RT5665_MONO_ADC_R_BST_SFT 12
594 #define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
595 #define RT5665_STO2_ADC_R_BST_SFT 12
602 #define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)
603 #define RT5665_STO1_ADC1L_SRC_SFT 13
604 #define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)
605 #define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13)
606 #define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
607 #define RT5665_STO1_ADC2L_SRC_SFT 12
635 #define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)
636 #define RT5665_MONO_ADC_L1_SRC_SFT 13
637 #define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
638 #define RT5665_MONO_ADC_L2_SRC_SFT 12
666 #define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)
667 #define RT5665_STO2_ADC1L_SRC_SFT 13
668 #define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)
669 #define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13)
670 #define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
671 #define RT5665_STO2_ADC2L_SRC_SFT 12
713 #define RT5665_M_DAC_R1_STO_L (0x1 << 13)
714 #define RT5665_M_DAC_R1_STO_L_SFT 13
715 #define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
716 #define RT5665_G_DAC_R1_STO_L_SFT 12
747 #define RT5665_M_DAC_R1_MONO_L (0x1 << 13)
748 #define RT5665_M_DAC_R1_MONO_L_SFT 13
749 #define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
750 #define RT5665_G_DAC_R1_MONO_L_SFT 12
781 #define RT5665_M_DAC_L2_STO2_L (0x1 << 13)
782 #define RT5665_M_DAC_L2_STO2_L_SFT 13
783 #define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
784 #define RT5665_G_DAC_L2_STO2_L_SFT 12
807 #define RT5665_DAC_MIX_L_MASK (0x3 << 12)
808 #define RT5665_DAC_MIX_L_SFT 12
823 #define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
824 #define RT5665_IF2_1_ADC_IN_SFT 12
847 #define RT5665_M_PDM1_R (0x1 << 12)
848 #define RT5665_M_PDM1_R_SFT 12
952 #define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)
953 #define RT5665_M_DAC_L2_SPKOMIX_SFT 13
954 #define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
955 #define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
980 #define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
981 #define RT5665_G_BST3_OM_L_SFT 12
1020 #define RT5665_M_OV_L_LM (0x1 << 13)
1021 #define RT5665_M_OV_L_LM_SFT 13
1022 #define RT5665_M_OV_R_LM (0x1 << 12)
1023 #define RT5665_M_OV_R_LM_SFT 12
1033 #define RT5665_PWR_I2S2_1 (0x1 << 13)
1034 #define RT5665_PWR_I2S2_1_BIT 13
1035 #define RT5665_PWR_I2S2_2 (0x1 << 12)
1036 #define RT5665_PWR_I2S2_2_BIT 12
1063 #define RT5665_PWR_ADC_MF_L (0x1 << 13)
1064 #define RT5665_PWR_ADC_MF_L_BIT 13
1065 #define RT5665_PWR_ADC_MF_R (0x1 << 12)
1066 #define RT5665_PWR_ADC_MF_R_BIT 12
1083 #define RT5665_PWR_VREF2 (0x1 << 13)
1084 #define RT5665_PWR_VREF2_BIT 13
1085 #define RT5665_PWR_FV2 (0x1 << 12)
1086 #define RT5665_PWR_FV2_BIT 12
1118 #define RT5665_PWR_BST3 (0x1 << 13)
1119 #define RT5665_PWR_BST3_BIT 13
1120 #define RT5665_PWR_BST4 (0x1 << 12)
1121 #define RT5665_PWR_BST4_BIT 12
1166 #define RT5665_PWR_OM_L (0x1 << 13)
1167 #define RT5665_PWR_OM_L_BIT 13
1168 #define RT5665_PWR_OM_R (0x1 << 12)
1169 #define RT5665_PWR_OM_R_BIT 12
1188 #define RT5665_PWR_OV_L (0x1 << 13)
1189 #define RT5665_PWR_OV_L_BIT 13
1190 #define RT5665_PWR_OV_R (0x1 << 12)
1191 #define RT5665_PWR_OV_R_BIT 12
1204 #define RT5665_MONO_CLK_DET 13
1205 #define RT5665_LOUT_CLK_DET 12
1276 #define RT5665_I2S_PD1_MASK (0x7 << 12)
1277 #define RT5665_I2S_PD1_SFT 12
1278 #define RT5665_I2S_PD1_1 (0x0 << 12)
1279 #define RT5665_I2S_PD1_2 (0x1 << 12)
1280 #define RT5665_I2S_PD1_3 (0x2 << 12)
1281 #define RT5665_I2S_PD1_4 (0x3 << 12)
1282 #define RT5665_I2S_PD1_6 (0x4 << 12)
1283 #define RT5665_I2S_PD1_8 (0x5 << 12)
1284 #define RT5665_I2S_PD1_12 (0x6 << 12)
1285 #define RT5665_I2S_PD1_16 (0x7 << 12)
1317 #define RT5665_I2S_PD2_MASK (0x7 << 12)
1318 #define RT5665_I2S_PD2_SFT 12
1319 #define RT5665_I2S_PD2_1 (0x0 << 12)
1320 #define RT5665_I2S_PD2_2 (0x1 << 12)
1321 #define RT5665_I2S_PD2_3 (0x2 << 12)
1322 #define RT5665_I2S_PD2_4 (0x3 << 12)
1323 #define RT5665_I2S_PD2_6 (0x4 << 12)
1324 #define RT5665_I2S_PD2_8 (0x5 << 12)
1325 #define RT5665_I2S_PD2_12 (0x6 << 12)
1326 #define RT5665_I2S_PD2_16 (0x7 << 12)
1380 #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
1425 #define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
1426 #define RT5665_PLL_M_SFT 12
1437 #define RT5665_I2S1_ASRC_MASK (0x1 << 13)
1438 #define RT5665_I2S1_ASRC_SFT 13
1439 #define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
1440 #define RT5665_DAC_STO1_ASRC_SFT 12
1465 #define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
1466 #define RT5665_DA_STO1_CLK_SEL_SFT 12
1475 #define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
1476 #define RT5665_AD_STO1_CLK_SEL_SFT 12
1485 #define RT5665_I2S1_RATE_MASK (0xf << 12)
1486 #define RT5665_I2S1_RATE_SFT 12
1496 #define RT5665_DEPOP_MASK (0x1 << 13)
1497 #define RT5665_DEPOP_SFT 13
1498 #define RT5665_DEPOP_AUTO (0x0 << 13)
1499 #define RT5665_DEPOP_MAN (0x1 << 13)
1500 #define RT5665_RAMP_MASK (0x1 << 12)
1501 #define RT5665_RAMP_SFT 12
1502 #define RT5665_RAMP_DIS (0x0 << 12)
1503 #define RT5665_RAMP_EN (0x1 << 12)
1530 #define RT5665_CP_SYS_MASK (0x7 << 12)
1531 #define RT5665_CP_SYS_SFT 12
1587 #define RT5665_MIC1_CLK_MASK (0x1 << 13)
1588 #define RT5665_MIC1_CLK_SFT 13
1589 #define RT5665_MIC1_CLK_DIS (0x0 << 13)
1590 #define RT5665_MIC1_CLK_EN (0x1 << 13)
1591 #define RT5665_MIC2_CLK_MASK (0x1 << 12)
1592 #define RT5665_MIC2_CLK_SFT 12
1593 #define RT5665_MIC2_CLK_DIS (0x0 << 12)
1594 #define RT5665_MIC2_CLK_EN (0x1 << 12)
1640 #define RT5665_I2S2_SRC_MASK (0x3 << 12)
1641 #define RT5665_I2S2_SRC_SFT 12
1655 #define RT5665_EQ_CD_MASK (0x1 << 13)
1656 #define RT5665_EQ_CD_SFT 13
1657 #define RT5665_EQ_CD_DIS (0x0 << 13)
1658 #define RT5665_EQ_CD_EN (0x1 << 13)
1671 #define RT5665_JD1_2_EN_MASK (0x1 << 12)
1672 #define RT5665_JD1_2_EN_SFT 12
1673 #define RT5665_JD1_2_DIS (0x0 << 12)
1674 #define RT5665_JD1_2_EN (0x1 << 12)
1690 #define RT5665_GP2_PIN_MASK (0x3 << 13)
1691 #define RT5665_GP2_PIN_SFT 13
1692 #define RT5665_GP2_PIN_GPIO2 (0x0 << 13)
1693 #define RT5665_GP2_PIN_BCLK2 (0x1 << 13)
1694 #define RT5665_GP2_PIN_PDM_SCL (0x2 << 13)
1735 #define RT5665_GP10_PIN_MASK (0x3 << 12)
1736 #define RT5665_GP10_PIN_SFT 12
1737 #define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
1738 #define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
1739 #define RT5665_GP10_PIN_LPD (0x2 << 12)
1785 #define RT5665_GP8_PF_MASK (0x1 << 13)
1786 #define RT5665_GP8_PF_IN (0x0 << 13)
1787 #define RT5665_GP8_PF_OUT (0x1 << 13)
1788 #define RT5665_GP8_OUT_MASK (0x1 << 12)
1789 #define RT5665_GP8_OUT_H (0x0 << 12)
1790 #define RT5665_GP8_OUT_L (0x1 << 12)
1815 #define RT5665_OUT_SV_MASK (0x1 << 13)
1816 #define RT5665_OUT_SV_SFT 13
1817 #define RT5665_OUT_SV_DIS (0x0 << 13)
1818 #define RT5665_OUT_SV_EN (0x1 << 13)
1819 #define RT5665_HP_SV_MASK (0x1 << 12)
1820 #define RT5665_HP_SV_SFT 12
1821 #define RT5665_HP_SV_DIS (0x0 << 12)
1822 #define RT5665_HP_SV_EN (0x1 << 12)
1873 #define RT5665_M_RF_DIG_MASK (0x1 << 12)
1874 #define RT5665_M_RF_DIG_SFT 12
1878 #define RT5665_CKXEN_DAC1_MASK (0x1 << 13)
1879 #define RT5665_CKXEN_DAC1_SFT 13
1880 #define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
1881 #define RT5665_CKGEN_DAC1_SFT 12
1888 #define RT5665_CKXEN_ADC1_MASK (0x1 << 13)
1889 #define RT5665_CKXEN_ADC1_SFT 13
1890 #define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
1891 #define RT5665_CKGEN_ADC1_SFT 12
1922 #define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)
1923 #define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1924 #define RT5665_SAR_BUTDET_RST (0x0 << 13)
1925 #define RT5665_SAR_POW_MASK (0x1 << 12)
1926 #define RT5665_SAR_POW_EN (0x1 << 12)
1927 #define RT5665_SAR_POW_DIS (0x0 << 12)