Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
82 /* Function - Analog */
99 /* Function - Digital */
235 #define RT5651_SEL_DAC_L2 (0x1 << 11)
236 #define RT5651_IF2_DAC_L2 (0x1 << 11)
237 #define RT5651_IF1_DAC_L2 (0x0 << 11)
238 #define RT5651_SEL_DAC_L2_SFT 11
239 #define RT5651_SEL_DAC_R2 (0x1 << 10)
240 #define RT5651_IF2_DAC_R2 (0x1 << 11)
241 #define RT5651_IF1_DAC_R2 (0x0 << 11)
242 #define RT5651_SEL_DAC_R2_SFT 10
265 #define RT5651_ADC_COMP_MASK (0x3 << 10)
266 #define RT5651_ADC_COMP_SFT 10
277 #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
278 #define RT5651_STO1_ADC_2_SRC_SFT 11
279 #define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
280 #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
295 #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
296 #define RT5651_STO2_ADC_L2_SRC_SFT 11
297 #define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
298 #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
329 #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
330 #define RT5651_DAC_L2_STO_L_VOL_SFT 11
355 #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
356 #define RT5651_STO_DD_L2_VOL_SFT 11
357 #define RT5651_M_STO_DD_R2_L (0x1 << 10)
358 #define RT5651_M_STO_DD_R2_L_SFT 10
383 #define RT5651_M_STO_R_DAC_R (0x1 << 11)
384 #define RT5651_M_STO_R_DAC_R_SFT 11
385 #define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
386 #define RT5651_STO_R_DAC_R_VOL_SFT 10
414 #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
415 #define RT5651_IF2_ADC_L_SEL_SFT 11
416 #define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
417 #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
418 #define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
419 #define RT5651_IF2_ADC_R_SEL_SFT 10
420 #define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
421 #define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
448 #define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
449 #define RT5651_IF2_DAC_SEL_SFT 10
450 #define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
451 #define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
452 #define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
453 #define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
494 #define PT5631_PDM_CMD_EXE (0x1 << 11)
495 #define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
496 #define RT5651_PDM_I2C_CMD_R (0x0 << 10)
497 #define RT5651_PDM_I2C_CMD_W (0x1 << 10)
510 #define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
511 #define RT5651_G_IN_L1_RM_L_SFT 10
520 #define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
521 #define RT5651_G_OM_L_RM_L_SFT 10
538 #define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
539 #define RT5651_G_IN1_R_RM_R_SFT 10
548 #define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
549 #define RT5651_G_OM_R_RM_R_SFT 10
576 #define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
577 #define RT5651_G_DAC_L1_SM_L_SFT 10
598 #define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
599 #define RT5651_G_DAC_R1_SM_R_SFT 10
624 #define RT5651_M_BST1_SPM_L (0x1 << 11)
625 #define RT5651_M_BST1_SPM_L_SFT 11
632 #define RT5651_M_BST1_SPM_R (0x1 << 11)
633 #define RT5651_M_BST1_SPM_R_SFT 11
648 #define RT5651_M_BST1_MM (0x1 << 11)
649 #define RT5651_M_BST1_MM_SFT 11
650 #define RT5651_G_MONOMIX_MASK (0x1 << 10)
651 #define RT5651_G_MONOMIX_SFT 10
654 #define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
655 #define RT5651_G_BST2_OM_L_SFT 10
684 #define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
685 #define RT5651_G_BST2_OM_R_SFT 10
722 #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
723 #define RT5651_G_LOUTMIX_SFT 11
732 #define RT5651_PWR_DAC_R1 (0x1 << 11)
733 #define RT5651_PWR_DAC_R1_BIT 11
744 #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
745 #define RT5651_PWR_DAC_STO1_F_BIT 11
746 #define RT5651_PWR_DAC_STO2_F (0x1 << 10)
747 #define RT5651_PWR_DAC_STO2_F_BIT 10
760 #define RT5651_PWR_BG (0x1 << 11)
761 #define RT5651_PWR_BG_BIT 11
787 #define RT5651_PWR_MB1 (0x1 << 11)
788 #define RT5651_PWR_MB1_BIT 11
809 #define RT5651_PWR_RM_L (0x1 << 11)
810 #define RT5651_PWR_RM_L_BIT 11
811 #define RT5651_PWR_RM_R (0x1 << 10)
812 #define RT5651_PWR_RM_R_BIT 10
819 #define RT5651_PWR_HV_L (0x1 << 11)
820 #define RT5651_PWR_HV_L_BIT 11
821 #define RT5651_PWR_HV_R (0x1 << 10)
822 #define RT5651_PWR_HV_R_BIT 10
837 #define RT5651_I2S_O_CP_MASK (0x3 << 10)
838 #define RT5651_I2S_O_CP_SFT 10
839 #define RT5651_I2S_O_CP_OFF (0x0 << 10)
840 #define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
841 #define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
875 #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
876 #define RT5651_I2S_BCLK_MS2_SFT 11
877 #define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
878 #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
903 #define RT5651_DAHPF_EN (0x1 << 11)
904 #define RT5651_DAHPF_EN_SFT 11
905 #define RT5651_ADHPF_EN (0x1 << 10)
906 #define RT5651_ADHPF_EN_SFT 10
921 #define RT5651_DMIC_1_DP_MASK (0x3 << 10)
922 #define RT5651_DMIC_1_DP_SFT 10
923 #define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
924 #define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
925 #define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
944 #define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
945 #define RT5651_TDM_CH_LEN_SEL_SFT 10
946 #define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
947 #define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
948 #define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
949 #define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
996 #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
997 #define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
998 #define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
999 #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1000 #define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1001 #define RT5651_TDM_END_EDGE_SEL_SFT 10
1002 #define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1003 #define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1091 #define RT5651_PLL_M_BP (0x1 << 11)
1092 #define RT5651_PLL_M_BP_SFT 11
1103 #define RT5651_ASRC2_REF_MASK (0x1 << 11)
1104 #define RT5651_ASRC2_REF_SFT 11
1105 #define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1106 #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1125 #define RT5651_ADC_M_MASK (0x1 << 11)
1126 #define RT5651_ADC_M_SFT 11
1127 #define RT5651_ADC_M_NOR (0x0 << 11)
1128 #define RT5651_ADC_M_ASRC (0x1 << 11)
1174 #define RT5651_HP_OVCD_MASK (0x1 << 10)
1175 #define RT5651_HP_OVCD_SFT 10
1176 #define RT5651_HP_OVCD_DIS (0x0 << 10)
1177 #define RT5651_HP_OVCD_EN (0x1 << 10)
1240 #define RT5651_BPS_MASK (0x1 << 11)
1241 #define RT5651_BPS_SFT 11
1242 #define RT5651_BPS_DIS (0x0 << 11)
1243 #define RT5651_BPS_EN (0x1 << 11)
1244 #define RT5651_FAST_UPDN_MASK (0x1 << 10)
1245 #define RT5651_FAST_UPDN_SFT 10
1246 #define RT5651_FAST_UPDN_DIS (0x0 << 10)
1247 #define RT5651_FAST_UPDN_EN (0x1 << 10)
1284 #define RT5651_OSW_L_MASK (0x1 << 11)
1285 #define RT5651_OSW_L_SFT 11
1286 #define RT5651_OSW_L_DIS (0x0 << 11)
1287 #define RT5651_OSW_L_EN (0x1 << 11)
1288 #define RT5651_OSW_R_MASK (0x1 << 10)
1289 #define RT5651_OSW_R_SFT 10
1290 #define RT5651_OSW_R_DIS (0x0 << 10)
1291 #define RT5651_OSW_R_EN (0x1 << 10)
1313 #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1314 #define RT5651_MIC1_OVCD_SFT 11
1315 #define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1316 #define RT5651_MIC1_OVCD_EN (0x1 << 11)
1334 #define RT5651_JD_PU (0x1 << 11)
1335 #define RT5651_JD_PU_SFT 11
1336 #define RT5651_JD_PD (0x1 << 10)
1337 #define RT5651_JD_PD_SFT 10
1504 #define RT5651_JD_HP_MASK (0x1 << 11)
1505 #define RT5651_JD_HP_SFT 11
1506 #define RT5651_JD_HP_DIS (0x0 << 11)
1507 #define RT5651_JD_HP_EN (0x1 << 11)
1508 #define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1509 #define RT5651_JD_HP_TRG_SFT 10
1510 #define RT5651_JD_HP_TRG_LO (0x0 << 10)
1511 #define RT5651_JD_HP_TRG_HI (0x1 << 10)
1561 #define RT5651_JD_P_MASK (0x1 << 11)
1562 #define RT5651_JD_P_SFT 11
1563 #define RT5651_JD_P_NOR (0x0 << 11)
1564 #define RT5651_JD_P_INV (0x1 << 11)
1589 #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1590 #define RT5651_MB1_OC_STKY_SFT 11
1591 #define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1592 #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1612 #define RT5651_STA_GP7 (0x1 << 11)
1613 #define RT5651_STA_GP7_BIT 11
1614 #define RT5651_STA_GP6 (0x1 << 10)
1615 #define RT5651_STA_GP6_BIT 10
1680 #define RT5651_GP4_DR_MASK (0x1 << 11)
1681 #define RT5651_GP4_DR_SFT 11
1682 #define RT5651_GP4_DR_IN (0x0 << 11)
1683 #define RT5651_GP4_DR_OUT (0x1 << 11)
1684 #define RT5651_GP4_OUT_MASK (0x1 << 10)
1685 #define RT5651_GP4_OUT_SFT 10
1686 #define RT5651_GP4_OUT_LO (0x0 << 10)
1687 #define RT5651_GP4_OUT_HI (0x1 << 10)
1842 #define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1843 #define RT5651_3D_1F_MIX_SFT 11
1844 #define RT5651_3D_HP_M_MASK (0x1 << 10)
1845 #define RT5651_3D_HP_M_SFT 10
1846 #define RT5651_3D_HP_M_SUR (0x0 << 10)
1847 #define RT5651_3D_HP_M_FRO (0x1 << 10)
1882 #define RT5651_SI_DAC_MASK (0x1 << 11)
1883 #define RT5651_SI_DAC_SFT 11
1884 #define RT5651_SI_DAC_AUTO (0x0 << 11)
1885 #define RT5651_SI_DAC_TEST (0x1 << 11)
1886 #define RT5651_DC_CAL_M_MASK (0x1 << 10)
1887 #define RT5651_DC_CAL_M_SFT 10
1888 #define RT5651_DC_CAL_M_NOR (0x0 << 10)
1889 #define RT5651_DC_CAL_M_CAL (0x1 << 10)
1931 #define RT5651_ZCD_DIG_MASK (0x1 << 11)
1932 #define RT5651_ZCD_DIG_SFT 11
1933 #define RT5651_ZCD_DIG_DIS (0x0 << 11)
1934 #define RT5651_ZCD_DIG_EN (0x1 << 11)
1935 #define RT5651_ZCD_MASK (0x1 << 10)
1936 #define RT5651_ZCD_SFT 10
1937 #define RT5651_ZCD_PD (0x0 << 10)
1938 #define RT5651_ZCD_PU (0x1 << 10)
1995 #define RT5651_WND_FC_NW_MASK (0x3f << 10)
1996 #define RT5651_WND_FC_NW_SFT 10
2015 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2028 #define RT5651_DP_SPK_MASK (0x1 << 10)
2029 #define RT5651_DP_SPK_SFT 10
2030 #define RT5651_DP_SPK_DIS (0x0 << 10)
2031 #define RT5651_DP_SPK_EN (0x1 << 10)