Lines Matching +full:12 +full:- +full:13
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
99 /* Format - TDM Control */
105 /* Function - Analog */
121 /* Function - Digital */
231 #define RT5645_CBJ_BST1_MASK (0xf << 12)
232 #define RT5645_CBJ_BST1_SFT (12)
242 #define RT5645_CBJ_MN_JD (0x1 << 12)
251 #define RT5645_BST_MASK1 (0xf<<12)
252 #define RT5645_BST_SFT1 12
285 #define RT5645_M_DAC_L2_VOL (0x1 << 13)
286 #define RT5645_M_DAC_L2_VOL_SFT 13
287 #define RT5645_M_DAC_R2_VOL (0x1 << 12)
288 #define RT5645_M_DAC_R2_VOL_SFT 12
309 #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
310 #define RT5645_STO1_ADC_R_BST_SFT 12
317 #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)
318 #define RT5645_MONO_ADC_R_BST_SFT 12
329 #define RT5645_M_ADC_L2 (0x1 << 13)
330 #define RT5645_M_ADC_L2_SFT 13
331 #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
332 #define RT5645_ADC_1_SRC_SFT 12
333 #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
334 #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
349 #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
350 #define RT5645_M_MONO_ADC_L2_SFT 13
351 #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
352 #define RT5645_MONO_ADC_L1_SRC_SFT 12
353 #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
354 #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
397 #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
398 #define RT5645_DAC_L1_STO_L_VOL_SFT 13
399 #define RT5645_M_DAC_L2 (0x1 << 12)
400 #define RT5645_M_DAC_L2_SFT 12
427 #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
428 #define RT5645_DAC_L1_MONO_L_VOL_SFT 13
429 #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
430 #define RT5645_M_DAC_L2_MONO_L_SFT 12
455 #define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
456 #define RT5645_M_DAC_L2_DAC_L_SFT 13
457 #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
458 #define RT5645_DAC_L2_DAC_L_VOL_SFT 12
485 #define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
486 #define RT5645_IF2_ADC_IN_SFT 12
503 #define RT5645_PDM1_R_MASK (0x1 << 13)
504 #define RT5645_PDM1_R_SFT 13
505 #define RT5645_M_PDM1_R (0x1 << 12)
506 #define RT5645_M_PDM1_R_SFT 12
522 #define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
523 #define RT5645_G_HP_L_RM_L_SFT 13
534 #define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
535 #define RT5645_G_BST1_RM_L_SFT 13
554 #define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
555 #define RT5645_G_HP_R_RM_R_SFT 13
566 #define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
567 #define RT5645_G_BST1_RM_R_SFT 13
602 #define RT5645_M_HPVOL_HM (0x1 << 13)
603 #define RT5645_M_HPVOL_HM_SFT 13
604 #define RT5645_IRQ_PSV_MODE (0x1 << 12)
609 #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
610 #define RT5645_G_IN_L_SM_L_SFT 12
631 #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
632 #define RT5645_G_IN_R_SM_R_SFT 12
655 #define RT5645_M_SV_L_SPM_L (0x1 << 13)
656 #define RT5645_M_SV_L_SPM_L_SFT 13
657 #define RT5645_M_SV_R_SPM_L (0x1 << 12)
658 #define RT5645_M_SV_R_SPM_L_SFT 12
691 #define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
692 #define RT5645_G_BST3_OM_L_SFT 13
703 #define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
704 #define RT5645_G_DAC_R2_OM_L_SFT 13
723 #define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
724 #define RT5645_G_BST4_OM_R_SFT 13
735 #define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
736 #define RT5645_G_DAC_L2_OM_R_SFT 13
759 #define RT5645_M_OV_L_LM (0x1 << 13)
760 #define RT5645_M_OV_L_LM_SFT 13
761 #define RT5645_M_OV_R_LM (0x1 << 12)
762 #define RT5645_M_OV_R_LM_SFT 12
771 #define RT5645_PWR_I2S3 (0x1 << 13)
772 #define RT5645_PWR_I2S3_BIT 13
773 #define RT5645_PWR_DAC_L1 (0x1 << 12)
774 #define RT5645_PWR_DAC_L1_BIT 12
797 #define RT5645_PWR_ADC_MF_R (0x1 << 13)
798 #define RT5645_PWR_ADC_MF_R_BIT 13
799 #define RT5645_PWR_I2S_DSP (0x1 << 12)
800 #define RT5645_PWR_I2S_DSP_BIT 12
821 #define RT5645_PWR_MB (0x1 << 13)
822 #define RT5645_PWR_MB_BIT 13
823 #define RT5645_PWR_LM (0x1 << 12)
824 #define RT5645_PWR_LM_BIT 12
847 #define RT5645_PWR_BST3 (0x1 << 13)
848 #define RT5645_PWR_BST3_BIT 13
849 #define RT5645_PWR_BST4 (0x1 << 12)
850 #define RT5645_PWR_BST4_BIT 12
873 #define RT5645_PWR_SM_L (0x1 << 13)
874 #define RT5645_PWR_SM_L_BIT 13
875 #define RT5645_PWR_SM_R (0x1 << 12)
876 #define RT5645_PWR_SM_R_BIT 12
945 #define RT5645_I2S_PD1_MASK (0x7 << 12)
946 #define RT5645_I2S_PD1_SFT 12
947 #define RT5645_I2S_PD1_1 (0x0 << 12)
948 #define RT5645_I2S_PD1_2 (0x1 << 12)
949 #define RT5645_I2S_PD1_3 (0x2 << 12)
950 #define RT5645_I2S_PD1_4 (0x3 << 12)
951 #define RT5645_I2S_PD1_6 (0x4 << 12)
952 #define RT5645_I2S_PD1_8 (0x5 << 12)
953 #define RT5645_I2S_PD1_12 (0x6 << 12)
954 #define RT5645_I2S_PD1_16 (0x7 << 12)
1003 #define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1004 #define RT5645_ADC_R_OSR_SFT 12
1005 #define RT5645_ADC_R_OSR_128 (0x0 << 12)
1006 #define RT5645_ADC_R_OSR_64 (0x1 << 12)
1007 #define RT5645_ADC_R_OSR_32 (0x2 << 12)
1008 #define RT5645_ADC_R_OSR_16 (0x3 << 12)
1023 #define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1024 #define RT5645_DMIC_1L_LH_SFT 13
1025 #define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
1026 #define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1027 #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1028 #define RT5645_DMIC_1R_LH_SFT 12
1029 #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1030 #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1091 #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1092 #define RT5645_PLL_M_SFT 12
1105 #define RT5645_I2S2_F_MASK (0x1 << 12)
1106 #define RT5645_I2S2_F_SFT 12
1107 #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1108 #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1125 #define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
1126 #define RT5645_DA_STO_CLK_SEL_SFT 12
1141 #define RT5645_I2S1_PD_MASK (0x7 << 12)
1142 #define RT5645_I2S1_PD_SFT 12
1171 #define RT5645_CLSD_RATIO_MASK (0xf << 12)
1172 #define RT5645_CLSD_RATIO_SFT 12
1229 #define RT5645_DEPOP_MASK (0x1 << 13)
1230 #define RT5645_DEPOP_SFT 13
1231 #define RT5645_DEPOP_AUTO (0x0 << 13)
1232 #define RT5645_DEPOP_MAN (0x1 << 13)
1233 #define RT5645_RAMP_MASK (0x1 << 12)
1234 #define RT5645_RAMP_SFT 12
1235 #define RT5645_RAMP_DIS (0x0 << 12)
1236 #define RT5645_RAMP_EN (0x1 << 12)
1263 #define RT5645_CP_SYS_MASK (0x7 << 12)
1264 #define RT5645_CP_SYS_SFT 12
1299 #define RT5645_MIC1_CLK_MASK (0x1 << 13)
1300 #define RT5645_MIC1_CLK_SFT 13
1301 #define RT5645_MIC1_CLK_DIS (0x0 << 13)
1302 #define RT5645_MIC1_CLK_EN (0x1 << 13)
1303 #define RT5645_MIC2_CLK_MASK (0x1 << 12)
1304 #define RT5645_MIC2_CLK_SFT 12
1305 #define RT5645_MIC2_CLK_DIS (0x0 << 12)
1306 #define RT5645_MIC2_CLK_EN (0x1 << 12)
1351 #define RT5645_EQ_CD_MASK (0x1 << 13)
1352 #define RT5645_EQ_CD_SFT 13
1353 #define RT5645_EQ_CD_DIS (0x0 << 13)
1354 #define RT5645_EQ_CD_EN (0x1 << 13)
1416 #define RT5645_DRC_AGC_UPD (0x1 << 13)
1417 #define RT5645_DRC_AGC_UPD_BIT 13
1448 #define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1449 #define RT5645_DRC_AGC_NGB_SFT 12
1472 #define RT5645_ANC_MD_MASK (0x3 << 12)
1473 #define RT5645_ANC_MD_SFT 12
1474 #define RT5645_ANC_MD_DIS (0x0 << 12)
1475 #define RT5645_ANC_MD_67MS (0x1 << 12)
1476 #define RT5645_ANC_MD_267MS (0x2 << 12)
1477 #define RT5645_ANC_MD_1067MS (0x3 << 12)
1504 #define RT5645_ANC_FG_R_MASK (0xf << 12)
1505 #define RT5645_ANC_FG_R_SFT 12
1522 #define RT5645_JD_MASK (0x7 << 13)
1523 #define RT5645_JD_SFT 13
1524 #define RT5645_JD_DIS (0x0 << 13)
1525 #define RT5645_JD_GPIO1 (0x1 << 13)
1526 #define RT5645_JD_JD1_IN4P (0x2 << 13)
1527 #define RT5645_JD_JD2_IN4N (0x3 << 13)
1528 #define RT5645_JD_GPIO2 (0x4 << 13)
1529 #define RT5645_JD_GPIO3 (0x5 << 13)
1530 #define RT5645_JD_GPIO4 (0x6 << 13)
1611 #define RT5645_JD_STKY_MASK (0x1 << 13)
1612 #define RT5645_JD_STKY_SFT 13
1613 #define RT5645_JD_STKY_DIS (0x0 << 13)
1614 #define RT5645_JD_STKY_EN (0x1 << 13)
1615 #define RT5645_OT_STKY_MASK (0x1 << 12)
1616 #define RT5645_OT_STKY_SFT 12
1617 #define RT5645_OT_STKY_DIS (0x0 << 12)
1618 #define RT5645_OT_STKY_EN (0x1 << 12)
1642 #define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1643 #define RT5645_MB1_OC_STKY_SFT 13
1644 #define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
1645 #define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1646 #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1647 #define RT5645_MB2_OC_STKY_SFT 12
1648 #define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1649 #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1672 #define RT5645_GP3_PIN_MASK (0x3 << 12)
1673 #define RT5645_GP3_PIN_SFT 12
1674 #define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1675 #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1676 #define RT5645_GP3_PIN_IRQ (0x2 << 12)
1771 #define RT5645_REG_SEQ_MASK (0xf << 12)
1772 #define RT5645_REG_SEQ_SFT 12
1837 #define RT5645_BB_CT_MASK (0x7 << 12)
1838 #define RT5645_BB_CT_SFT 12
1839 #define RT5645_BB_CT_A (0x0 << 12)
1840 #define RT5645_BB_CT_B (0x1 << 12)
1841 #define RT5645_BB_CT_C (0x2 << 12)
1842 #define RT5645_BB_CT_D (0x3 << 12)
1860 #define RT5645_M_MP3_MASK (0x1 << 13)
1861 #define RT5645_M_MP3_SFT 13
1862 #define RT5645_M_MP3_DIS (0x0 << 13)
1863 #define RT5645_M_MP3_EN (0x1 << 13)
1876 #define RT5645_MP3_WT_MASK (0x1 << 13)
1877 #define RT5645_MP3_WT_SFT 13
1878 #define RT5645_MP3_WT_1_4 (0x0 << 13)
1879 #define RT5645_MP3_WT_1_2 (0x1 << 13)
1894 #define RT5645_3D_BT_MASK (0x1 << 13)
1895 #define RT5645_3D_BT_SFT 13
1896 #define RT5645_3D_BT_DIS (0x0 << 13)
1897 #define RT5645_3D_BT_EN (0x1 << 13)
1918 #define RT5645_HPF_CF_L_MASK (0x7 << 12)
1919 #define RT5645_HPF_CF_L_SFT 12
1981 #define RT5645_OUT_SV_MASK (0x1 << 13)
1982 #define RT5645_OUT_SV_SFT 13
1983 #define RT5645_OUT_SV_DIS (0x0 << 13)
1984 #define RT5645_OUT_SV_EN (0x1 << 13)
1985 #define RT5645_HP_SV_MASK (0x1 << 12)
1986 #define RT5645_HP_SV_SFT 12
1987 #define RT5645_HP_SV_DIS (0x0 << 12)
1988 #define RT5645_HP_SV_EN (0x1 << 12)
2030 #define RT5645_3D_SPK_M_MASK (0x3 << 13)
2031 #define RT5645_3D_SPK_M_SFT 13
2064 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2065 #define RT5645_WND_WIND_SFT 13
2066 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2067 #define RT5645_WND_STRONG_SFT 12
2091 #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2107 #define RT5645_RST_DSP (0x1 << 13)
2108 #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2109 #define RT5645_IF1_ADC1_IN1_SFT 12
2133 #define RT5645_JD_PSV_MODE (0x1 << 12)