Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
99 /* Format - TDM Control */
105 /* Function - Analog */
121 /* Function - Digital */
243 #define RT5645_CAPLESS_EN (0x1 << 11)
311 #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
312 #define RT5645_STO1_ADC_COMP_SFT 10
319 #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
320 #define RT5645_MONO_ADC_COMP_SFT 10
335 #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
336 #define RT5645_ADC_2_SRC_SFT 11
355 #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
356 #define RT5645_MONO_ADC_L2_SRC_SFT 11
377 #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
378 #define RT5645_DAC1_R_SEL_SFT 10
379 #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
380 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
381 #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
382 #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
401 #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
402 #define RT5645_DAC_L2_STO_L_VOL_SFT 11
403 #define RT5645_M_ANC_DAC_L (0x1 << 10)
404 #define RT5645_M_ANC_DAC_L_SFT 10
431 #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
432 #define RT5645_DAC_L2_MONO_L_VOL_SFT 11
433 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
434 #define RT5645_M_DAC_R2_MONO_L_SFT 10
459 #define RT5645_M_STO_R_DAC_R (0x1 << 11)
460 #define RT5645_M_STO_R_DAC_R_SFT 11
461 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
462 #define RT5645_STO_R_DAC_R_VOL_SFT 10
487 #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
488 #define RT5645_IF2_DAC_SEL_SFT 10
507 #define RT5645_PDM2_L_MASK (0x1 << 11)
508 #define RT5645_PDM2_L_SFT 11
509 #define RT5645_M_PDM2_L (0x1 << 10)
510 #define RT5645_M_PDM2_L_SFT 10
524 #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
525 #define RT5645_G_IN_L_RM_L_SFT 10
536 #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
537 #define RT5645_G_OM_L_RM_L_SFT 10
556 #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
557 #define RT5645_G_IN_R_RM_R_SFT 10
568 #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
569 #define RT5645_G_OM_R_RM_R_SFT 10
611 #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
612 #define RT5645_G_DAC_L1_SM_L_SFT 10
633 #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
634 #define RT5645_G_DAC_R1_SM_R_SFT 10
659 #define RT5645_M_BST3_SPM_L (0x1 << 11)
660 #define RT5645_M_BST3_SPM_L_SFT 11
673 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
674 #define RT5645_G_MONOMIX_SFT 10
693 #define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
694 #define RT5645_G_BST2_OM_L_SFT 10
705 #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
706 #define RT5645_G_DAC_L2_OM_L_SFT 10
725 #define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
726 #define RT5645_G_BST2_OM_R_SFT 10
737 #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
738 #define RT5645_G_DAC_R2_OM_R_SFT 10
763 #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
764 #define RT5645_G_LOUTMIX_SFT 11
775 #define RT5645_PWR_DAC_R1 (0x1 << 11)
776 #define RT5645_PWR_DAC_R1_BIT 11
801 #define RT5645_PWR_DAC_S1F (0x1 << 11)
802 #define RT5645_PWR_DAC_S1F_BIT 11
803 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
804 #define RT5645_PWR_DAC_MF_L_BIT 10
825 #define RT5645_PWR_BG (0x1 << 11)
826 #define RT5645_PWR_BG_BIT 11
827 #define RT5645_PWR_MA (0x1 << 10)
828 #define RT5645_PWR_MA_BIT 10
851 #define RT5645_PWR_MB1 (0x1 << 11)
852 #define RT5645_PWR_MB1_BIT 11
853 #define RT5645_PWR_MB2 (0x1 << 10)
854 #define RT5645_PWR_MB2_BIT 10
877 #define RT5645_PWR_RM_L (0x1 << 11)
878 #define RT5645_PWR_RM_L_BIT 11
879 #define RT5645_PWR_RM_R (0x1 << 10)
880 #define RT5645_PWR_RM_R_BIT 10
895 #define RT5645_PWR_HV_L (0x1 << 11)
896 #define RT5645_PWR_HV_L_BIT 11
897 #define RT5645_PWR_HV_R (0x1 << 10)
898 #define RT5645_PWR_HV_R_BIT 10
911 #define RT5645_I2S_O_CP_MASK (0x3 << 10)
912 #define RT5645_I2S_O_CP_SFT 10
913 #define RT5645_I2S_O_CP_OFF (0x0 << 10)
914 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
915 #define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
955 #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
956 #define RT5645_I2S_BCLK_MS2_SFT 11
957 #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
958 #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
1009 #define RT5645_DAHPF_EN (0x1 << 11)
1010 #define RT5645_DAHPF_EN_SFT 11
1011 #define RT5645_ADHPF_EN (0x1 << 10)
1012 #define RT5645_ADHPF_EN_SFT 10
1031 #define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1032 #define RT5645_DMIC_2_DP_SFT 10
1033 #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1034 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1035 #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1036 #define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1067 #define RT5645_PLL1_SRC_MASK (0x7 << 11)
1068 #define RT5645_PLL1_SRC_SFT 11
1069 #define RT5645_PLL1_SRC_MCLK (0x0 << 11)
1070 #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1071 #define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)
1072 #define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)
1073 #define RT5645_PLL1_SRC_RCCLK (0x4 << 11)
1093 #define RT5645_PLL_M_BP (0x1 << 11)
1094 #define RT5645_PLL_M_BP_SFT 11
1147 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1148 #define RT5645_HP_OVCD_SFT 10
1149 #define RT5645_HP_OVCD_DIS (0x0 << 10)
1150 #define RT5645_HP_OVCD_EN (0x1 << 10)
1173 #define RT5645_CLSD_OM_MASK (0x1 << 11)
1174 #define RT5645_CLSD_OM_SFT 11
1175 #define RT5645_CLSD_OM_MONO (0x0 << 11)
1176 #define RT5645_CLSD_OM_STO (0x1 << 11)
1177 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1178 #define RT5645_CLSD_SCH_SFT 10
1179 #define RT5645_CLSD_SCH_L (0x0 << 10)
1180 #define RT5645_CLSD_SCH_S (0x1 << 10)
1237 #define RT5645_BPS_MASK (0x1 << 11)
1238 #define RT5645_BPS_SFT 11
1239 #define RT5645_BPS_DIS (0x0 << 11)
1240 #define RT5645_BPS_EN (0x1 << 11)
1241 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1242 #define RT5645_FAST_UPDN_SFT 10
1243 #define RT5645_FAST_UPDN_DIS (0x0 << 10)
1244 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1307 #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1308 #define RT5645_MIC1_OVCD_SFT 11
1309 #define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1310 #define RT5645_MIC1_OVCD_EN (0x1 << 11)
1478 #define RT5645_ANC_SN_MASK (0x1 << 11)
1479 #define RT5645_ANC_SN_SFT 11
1480 #define RT5645_ANC_SN_DIS (0x0 << 11)
1481 #define RT5645_ANC_SN_EN (0x1 << 11)
1482 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1483 #define RT5645_ANC_CLK_SFT 10
1484 #define RT5645_ANC_CLK_ANC (0x0 << 10)
1485 #define RT5645_ANC_CLK_REG (0x1 << 10)
1531 #define RT5645_JD_HP_MASK (0x1 << 11)
1532 #define RT5645_JD_HP_SFT 11
1533 #define RT5645_JD_HP_DIS (0x0 << 11)
1534 #define RT5645_JD_HP_EN (0x1 << 11)
1535 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1536 #define RT5645_JD_HP_TRG_SFT 10
1537 #define RT5645_JD_HP_TRG_LO (0x0 << 10)
1538 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1619 #define RT5645_JD_P_MASK (0x1 << 11)
1620 #define RT5645_JD_P_SFT 11
1621 #define RT5645_JD_P_NOR (0x0 << 11)
1622 #define RT5645_JD_P_INV (0x1 << 11)
1623 #define RT5645_OT_P_MASK (0x1 << 10)
1624 #define RT5645_OT_P_SFT 10
1625 #define RT5645_OT_P_NOR (0x0 << 10)
1626 #define RT5645_OT_P_INV (0x1 << 10)
1677 #define RT5645_GP4_PIN_MASK (0x1 << 11)
1678 #define RT5645_GP4_PIN_SFT 11
1679 #define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1680 #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1681 #define RT5645_DP_SIG_MASK (0x1 << 10)
1682 #define RT5645_DP_SIG_SFT 10
1683 #define RT5645_DP_SIG_TEST (0x0 << 10)
1684 #define RT5645_DP_SIG_AP (0x1 << 10)
1721 #define RT5645_GP4_PF_MASK (0x1 << 11)
1722 #define RT5645_GP4_PF_SFT 11
1723 #define RT5645_GP4_PF_IN (0x0 << 11)
1724 #define RT5645_GP4_PF_OUT (0x1 << 11)
1725 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1726 #define RT5645_GP4_OUT_SFT 10
1727 #define RT5645_GP4_OUT_LO (0x0 << 10)
1728 #define RT5645_GP4_OUT_HI (0x1 << 10)
1773 #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1774 #define RT5645_SEQ1_ST_SFT 11
1775 #define RT5645_SEQ1_ST_RUN (0x0 << 11)
1776 #define RT5645_SEQ1_ST_FIN (0x1 << 11)
1777 #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1778 #define RT5645_SEQ2_ST_SFT 10
1779 #define RT5645_SEQ2_ST_RUN (0x0 << 10)
1780 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1898 #define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1899 #define RT5645_3D_1F_MIX_SFT 11
1900 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1901 #define RT5645_3D_HP_M_SFT 10
1902 #define RT5645_3D_HP_M_SUR (0x0 << 10)
1903 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1920 #define RT5645_1ST_HPF_MASK (0x1 << 11)
1921 #define RT5645_1ST_HPF_SFT 11
1922 #define RT5645_1ST_HPF_DIS (0x0 << 11)
1923 #define RT5645_1ST_HPF_EN (0x1 << 11)
1936 #define RT5645_SI_DAC_MASK (0x1 << 11)
1937 #define RT5645_SI_DAC_SFT 11
1938 #define RT5645_SI_DAC_AUTO (0x0 << 11)
1939 #define RT5645_SI_DAC_TEST (0x1 << 11)
1940 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1941 #define RT5645_DC_CAL_M_SFT 10
1942 #define RT5645_DC_CAL_M_CAL (0x0 << 10)
1943 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1989 #define RT5645_ZCD_DIG_MASK (0x1 << 11)
1990 #define RT5645_ZCD_DIG_SFT 11
1991 #define RT5645_ZCD_DIG_DIS (0x0 << 11)
1992 #define RT5645_ZCD_DIG_EN (0x1 << 11)
1993 #define RT5645_ZCD_MASK (0x1 << 10)
1994 #define RT5645_ZCD_SFT 10
1995 #define RT5645_ZCD_PD (0x0 << 10)
1996 #define RT5645_ZCD_PU (0x1 << 10)
2044 #define RT5645_WND_FC_NW_MASK (0x3f << 10)
2045 #define RT5645_WND_FC_NW_SFT 10
2064 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2066 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2077 #define RT5645_DP_SPK_MASK (0x1 << 10)
2078 #define RT5645_DP_SPK_SFT 10
2079 #define RT5645_DP_SPK_DIS (0x0 << 10)
2080 #define RT5645_DP_SPK_EN (0x1 << 10)
2110 #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2111 #define RT5645_IF1_ADC1_IN2_SFT 11
2112 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2113 #define RT5645_IF1_ADC2_IN1_SFT 10
2134 #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)