Lines Matching +full:12 +full:- +full:13
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
84 /* Function - Analog */
102 /* Function - Digital */
205 #define RT5640_BST_SFT1 12
239 #define RT5640_M_DAC_L2_VOL (0x1 << 13)
240 #define RT5640_M_DAC_L2_VOL_SFT 13
241 #define RT5640_M_DAC_R2_VOL (0x1 << 12)
242 #define RT5640_M_DAC_R2_VOL_SFT 12
259 #define RT5640_ADC_R_BST_MASK (0x3 << 12)
260 #define RT5640_ADC_R_BST_SFT 12
267 #define RT5640_M_ADC_L2 (0x1 << 13)
268 #define RT5640_M_ADC_L2_SFT 13
269 #define RT5640_ADC_1_SRC_MASK (0x1 << 12)
270 #define RT5640_ADC_1_SRC_SFT 12
271 #define RT5640_ADC_1_SRC_ADC (0x1 << 12)
272 #define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
286 #define RT5640_M_MONO_ADC_L2 (0x1 << 13)
287 #define RT5640_M_MONO_ADC_L2_SFT 13
288 #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
289 #define RT5640_MONO_ADC_L1_SRC_SFT 12
290 #define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
291 #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
324 #define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
325 #define RT5640_DAC_L1_STO_L_VOL_SFT 13
326 #define RT5640_M_DAC_L2 (0x1 << 12)
327 #define RT5640_M_DAC_L2_SFT 12
346 #define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
347 #define RT5640_DAC_L1_MONO_L_VOL_SFT 13
348 #define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
349 #define RT5640_M_DAC_L2_MONO_L_SFT 12
374 #define RT5640_M_DAC_L2_DAC_L (0x1 << 13)
375 #define RT5640_M_DAC_L2_DAC_L_SFT 13
376 #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
377 #define RT5640_DAC_L2_DAC_L_VOL_SFT 12
404 #define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
405 #define RT5640_DAC_R2_SEL_SFT 12
406 #define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
407 #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
408 #define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
449 #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
450 #define RT5640_IF1_ADC_SEL_SFT 12
451 #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
452 #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
453 #define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
454 #define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
481 #define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
482 #define RT5640_G_HP_L_RM_L_SFT 13
493 #define RT5640_G_BST1_RM_L_MASK (0x7 << 13)
494 #define RT5640_G_BST1_RM_L_SFT 13
513 #define RT5640_G_HP_R_RM_R_MASK (0x7 << 13)
514 #define RT5640_G_HP_R_RM_R_SFT 13
525 #define RT5640_G_BST1_RM_R_MASK (0x7 << 13)
526 #define RT5640_G_BST1_RM_R_SFT 13
549 #define RT5640_M_HPVOL_HM (0x1 << 13)
550 #define RT5640_M_HPVOL_HM_SFT 13
551 #define RT5640_G_HPOMIX_MASK (0x1 << 12)
552 #define RT5640_G_HPOMIX_SFT 12
557 #define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
558 #define RT5640_G_IN_L_SM_L_SFT 12
579 #define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
580 #define RT5640_G_IN_R_SM_R_SFT 12
603 #define RT5640_M_SV_R_SPM_L (0x1 << 13)
604 #define RT5640_M_SV_R_SPM_L_SFT 13
605 #define RT5640_M_SV_L_SPM_L (0x1 << 12)
606 #define RT5640_M_SV_L_SPM_L_SFT 12
611 #define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
612 #define RT5640_M_DAC_R1_SPM_R_SFT 13
613 #define RT5640_M_SV_R_SPM_R (0x1 << 12)
614 #define RT5640_M_SV_R_SPM_R_SFT 12
627 #define RT5640_M_OV_R_MM (0x1 << 13)
628 #define RT5640_M_OV_R_MM_SFT 13
629 #define RT5640_M_OV_L_MM (0x1 << 12)
630 #define RT5640_M_OV_L_MM_SFT 12
637 #define RT5640_G_BST3_OM_L_MASK (0x7 << 13)
638 #define RT5640_G_BST3_OM_L_SFT 13
649 #define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13)
650 #define RT5640_G_DAC_R2_OM_L_SFT 13
677 #define RT5640_G_BST4_OM_R_MASK (0x7 << 13)
678 #define RT5640_G_BST4_OM_R_SFT 13
689 #define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13)
690 #define RT5640_G_DAC_L2_OM_R_SFT 13
721 #define RT5640_M_OV_L_LM (0x1 << 13)
722 #define RT5640_M_OV_L_LM_SFT 13
723 #define RT5640_M_OV_R_LM (0x1 << 12)
724 #define RT5640_M_OV_R_LM_SFT 12
733 #define RT5640_PWR_DAC_L1 (0x1 << 12)
734 #define RT5640_PWR_DAC_L1_BIT 12
753 #define RT5640_PWR_ADC_MF_R (0x1 << 13)
754 #define RT5640_PWR_ADC_MF_R_BIT 13
755 #define RT5640_PWR_I2S_DSP (0x1 << 12)
756 #define RT5640_PWR_I2S_DSP_BIT 12
763 #define RT5640_PWR_MB (0x1 << 13)
764 #define RT5640_PWR_MB_BIT 13
765 #define RT5640_PWR_LM (0x1 << 12)
766 #define RT5640_PWR_LM_BIT 12
791 #define RT5640_PWR_BST3 (0x1 << 13)
792 #define RT5640_PWR_BST3_BIT 13
793 #define RT5640_PWR_BST4 (0x1 << 12)
794 #define RT5640_PWR_BST4_BIT 12
805 #define RT5640_PWR_SM_L (0x1 << 13)
806 #define RT5640_PWR_SM_L_BIT 13
807 #define RT5640_PWR_SM_R (0x1 << 12)
808 #define RT5640_PWR_SM_R_BIT 12
819 #define RT5640_PWR_OV_L (0x1 << 13)
820 #define RT5640_PWR_OV_L_BIT 13
821 #define RT5640_PWR_OV_R (0x1 << 12)
822 #define RT5640_PWR_OV_R_BIT 12
837 #define RT5640_I2S_IF_MASK (0x7 << 12)
838 #define RT5640_I2S_IF_SFT 12
877 #define RT5640_I2S_PD1_MASK (0x7 << 12)
878 #define RT5640_I2S_PD1_SFT 12
879 #define RT5640_I2S_PD1_1 (0x0 << 12)
880 #define RT5640_I2S_PD1_2 (0x1 << 12)
881 #define RT5640_I2S_PD1_3 (0x2 << 12)
882 #define RT5640_I2S_PD1_4 (0x3 << 12)
883 #define RT5640_I2S_PD1_6 (0x4 << 12)
884 #define RT5640_I2S_PD1_8 (0x5 << 12)
885 #define RT5640_I2S_PD1_12 (0x6 << 12)
886 #define RT5640_I2S_PD1_16 (0x7 << 12)
935 #define RT5640_ADC_R_OSR_MASK (0x3 << 12)
936 #define RT5640_ADC_R_OSR_SFT 12
937 #define RT5640_ADC_R_OSR_128 (0x0 << 12)
938 #define RT5640_ADC_R_OSR_64 (0x1 << 12)
939 #define RT5640_ADC_R_OSR_32 (0x2 << 12)
940 #define RT5640_ADC_R_OSR_16 (0x3 << 12)
955 #define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
956 #define RT5640_DMIC_1L_LH_SFT 13
957 #define RT5640_DMIC_1L_LH_FALLING (0x0 << 13)
958 #define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
959 #define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
960 #define RT5640_DMIC_1R_LH_SFT 12
961 #define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
962 #define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
988 #define RT5640_PLL1_SRC_MASK (0x3 << 12)
989 #define RT5640_PLL1_SRC_SFT 12
990 #define RT5640_PLL1_SRC_MCLK (0x0 << 12)
991 #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
992 #define RT5640_PLL1_SRC_BCLK2 (0x2 << 12)
993 #define RT5640_PLL1_SRC_BCLK3 (0x3 << 12)
1011 #define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12)
1012 #define RT5640_PLL_M_SFT 12
1025 #define RT5640_I2S2_F_MASK (0x1 << 12)
1026 #define RT5640_I2S2_F_SFT 12
1027 #define RT5640_I2S2_F_I2S2_D2 (0x0 << 12)
1028 #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1051 #define RT5640_MAD_L_M_MASK (0x1 << 13)
1052 #define RT5640_MAD_L_M_SFT 13
1053 #define RT5640_MAD_L_M_NOR (0x0 << 13)
1054 #define RT5640_MAD_L_M_ASYN (0x1 << 13)
1055 #define RT5640_MAD_R_M_MASK (0x1 << 12)
1056 #define RT5640_MAD_R_M_SFT 12
1057 #define RT5640_MAD_R_M_NOR (0x0 << 12)
1058 #define RT5640_MAD_R_M_ASYN (0x1 << 12)
1082 #define RT5640_I2S1_RATE_MASK (0xf << 12)
1083 #define RT5640_I2S1_RATE_SFT 12
1088 #define RT5640_I2S1_PD_MASK (0x7 << 12)
1089 #define RT5640_I2S1_PD_SFT 12
1118 #define RT5640_CLSD_RATIO_MASK (0xf << 12)
1119 #define RT5640_CLSD_RATIO_SFT 12
1176 #define RT5640_DEPOP_MASK (0x1 << 13)
1177 #define RT5640_DEPOP_SFT 13
1178 #define RT5640_DEPOP_AUTO (0x0 << 13)
1179 #define RT5640_DEPOP_MAN (0x1 << 13)
1180 #define RT5640_RAMP_MASK (0x1 << 12)
1181 #define RT5640_RAMP_SFT 12
1182 #define RT5640_RAMP_DIS (0x0 << 12)
1183 #define RT5640_RAMP_EN (0x1 << 12)
1210 #define RT5640_CP_SYS_MASK (0x7 << 12)
1211 #define RT5640_CP_SYS_SFT 12
1267 #define RT5640_MIC1_CLK_MASK (0x1 << 13)
1268 #define RT5640_MIC1_CLK_SFT 13
1269 #define RT5640_MIC1_CLK_DIS (0x0 << 13)
1270 #define RT5640_MIC1_CLK_EN (0x1 << 13)
1271 #define RT5640_MIC2_CLK_MASK (0x1 << 12)
1272 #define RT5640_MIC2_CLK_SFT 12
1273 #define RT5640_MIC2_CLK_DIS (0x0 << 12)
1274 #define RT5640_MIC2_CLK_EN (0x1 << 12)
1309 #define RT5640_EQ_CD_MASK (0x1 << 13)
1310 #define RT5640_EQ_CD_SFT 13
1311 #define RT5640_EQ_CD_DIS (0x0 << 13)
1312 #define RT5640_EQ_CD_EN (0x1 << 13)
1373 #define RT5640_DRC_AGC_UPD (0x1 << 13)
1374 #define RT5640_DRC_AGC_UPD_BIT 13
1405 #define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
1406 #define RT5640_DRC_AGC_NGB_SFT 12
1429 #define RT5640_ANC_MD_MASK (0x3 << 12)
1430 #define RT5640_ANC_MD_SFT 12
1431 #define RT5640_ANC_MD_DIS (0x0 << 12)
1432 #define RT5640_ANC_MD_67MS (0x1 << 12)
1433 #define RT5640_ANC_MD_267MS (0x2 << 12)
1434 #define RT5640_ANC_MD_1067MS (0x3 << 12)
1461 #define RT5640_ANC_FG_R_MASK (0xf << 12)
1462 #define RT5640_ANC_FG_R_SFT 12
1479 #define RT5640_JD_MASK (0x7 << 13)
1480 #define RT5640_JD_SFT 13
1481 #define RT5640_JD_DIS (0x0 << 13)
1482 #define RT5640_JD_GPIO1 (0x1 << 13)
1483 #define RT5640_JD_JD1_IN4P (0x2 << 13)
1484 #define RT5640_JD_JD2_IN4N (0x3 << 13)
1485 #define RT5640_JD_GPIO2 (0x4 << 13)
1486 #define RT5640_JD_GPIO3 (0x5 << 13)
1487 #define RT5640_JD_GPIO4 (0x6 << 13)
1568 #define RT5640_JD_STKY_MASK (0x1 << 13)
1569 #define RT5640_JD_STKY_SFT 13
1570 #define RT5640_JD_STKY_DIS (0x0 << 13)
1571 #define RT5640_JD_STKY_EN (0x1 << 13)
1572 #define RT5640_OT_STKY_MASK (0x1 << 12)
1573 #define RT5640_OT_STKY_SFT 12
1574 #define RT5640_OT_STKY_DIS (0x0 << 12)
1575 #define RT5640_OT_STKY_EN (0x1 << 12)
1631 #define RT5640_GP3_PIN_MASK (0x3 << 12)
1632 #define RT5640_GP3_PIN_SFT 12
1633 #define RT5640_GP3_PIN_GPIO3 (0x0 << 12)
1634 #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1635 #define RT5640_GP3_PIN_IRQ (0x2 << 12)
1699 /* FM34-500 Register Control 1 (0xc4) */
1702 /* FM34-500 Register Control 2 (0xc5) */
1705 /* FM34-500 Register Control 3 (0xc6) */
1712 #define RT5640_DSP_CLK_MASK (0x3 << 12)
1713 #define RT5640_DSP_CLK_SFT 12
1714 #define RT5640_DSP_CLK_384K (0x0 << 12)
1715 #define RT5640_DSP_CLK_192K (0x1 << 12)
1716 #define RT5640_DSP_CLK_96K (0x2 << 12)
1717 #define RT5640_DSP_CLK_64K (0x3 << 12)
1738 #define RT5640_REG_SEQ_MASK (0xf << 12)
1739 #define RT5640_REG_SEQ_SFT 12
1804 #define RT5640_BB_CT_MASK (0x7 << 12)
1805 #define RT5640_BB_CT_SFT 12
1806 #define RT5640_BB_CT_A (0x0 << 12)
1807 #define RT5640_BB_CT_B (0x1 << 12)
1808 #define RT5640_BB_CT_C (0x2 << 12)
1809 #define RT5640_BB_CT_D (0x3 << 12)
1826 #define RT5640_M_MP3_MASK (0x1 << 13)
1827 #define RT5640_M_MP3_SFT 13
1828 #define RT5640_M_MP3_DIS (0x0 << 13)
1829 #define RT5640_M_MP3_EN (0x1 << 13)
1842 #define RT5640_MP3_WT_MASK (0x1 << 13)
1843 #define RT5640_MP3_WT_SFT 13
1844 #define RT5640_MP3_WT_1_4 (0x0 << 13)
1845 #define RT5640_MP3_WT_1_2 (0x1 << 13)
1860 #define RT5640_3D_BT_MASK (0x1 << 13)
1861 #define RT5640_3D_BT_SFT 13
1862 #define RT5640_3D_BT_DIS (0x0 << 13)
1863 #define RT5640_3D_BT_EN (0x1 << 13)
1884 #define RT5640_HPF_CF_L_MASK (0x7 << 12)
1885 #define RT5640_HPF_CF_L_SFT 12
1947 #define RT5640_OUT_SV_MASK (0x1 << 13)
1948 #define RT5640_OUT_SV_SFT 13
1949 #define RT5640_OUT_SV_DIS (0x0 << 13)
1950 #define RT5640_OUT_SV_EN (0x1 << 13)
1951 #define RT5640_HP_SV_MASK (0x1 << 12)
1952 #define RT5640_HP_SV_SFT 12
1953 #define RT5640_HP_SV_DIS (0x0 << 12)
1954 #define RT5640_HP_SV_EN (0x1 << 12)
1983 #define RT5640_M_MONO_ADC_L (0x1 << 13)
1984 #define RT5640_M_MONO_ADC_L_SFT 13
1985 #define RT5640_M_MONO_ADC_R (0x1 << 12)
1986 #define RT5640_M_MONO_ADC_R_SFT 12
1990 #define RT5640_IRQ_JD2_MASK (0x1 << 12)
1991 #define RT5640_IRQ_JD2_SFT 12
1992 #define RT5640_IRQ_JD2_BP (0x0 << 12)
1993 #define RT5640_IRQ_JD2_NOR (0x1 << 12)
2018 #define RT5640_3D_SPK_M_MASK (0x3 << 13)
2019 #define RT5640_3D_SPK_M_SFT 13
2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2053 #define RT5640_WND_WIND_SFT 13
2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2055 #define RT5640_WND_STRONG_SFT 12