Lines Matching full:null
115 SND_SOC_DAPM_SUPPLY("LDO Regulator", RK817_CODEC_AREF_RTCFG1, 6, 0, NULL, 0),
116 SND_SOC_DAPM_SUPPLY("IBIAS Block", RK817_CODEC_AREF_RTCFG1, 2, 1, NULL, 0),
117 SND_SOC_DAPM_SUPPLY("VAvg Buffer", RK817_CODEC_AREF_RTCFG1, 1, 1, NULL, 0),
118 SND_SOC_DAPM_SUPPLY("PLL Power", RK817_CODEC_APLL_CFG5, 0, 1, NULL, 0),
119 SND_SOC_DAPM_SUPPLY("I2S TX1 Transfer Start", RK817_CODEC_DI2S_RXCMD_TSD, 5, 0, NULL, 0),
122 SND_SOC_DAPM_SUPPLY("ADC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 7, 0, NULL, 0),
123 SND_SOC_DAPM_SUPPLY("I2S TX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 6, 0, NULL, 0),
124 SND_SOC_DAPM_SUPPLY("ADC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 5, 0, NULL, 0),
125 SND_SOC_DAPM_SUPPLY("I2S TX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 4, 0, NULL, 0),
126 SND_SOC_DAPM_SUPPLY("MIC Power On", RK817_CODEC_AMIC_CFG0, 6, 1, NULL, 0),
127 SND_SOC_DAPM_SUPPLY("I2S TX3 Transfer Start", RK817_CODEC_DI2S_TXCR3_TXCMD, 7, 0, NULL, 0),
128 SND_SOC_DAPM_SUPPLY("I2S TX3 Right Justified", RK817_CODEC_DI2S_TXCR3_TXCMD, 3, 0, NULL, 0),
132 SND_SOC_DAPM_SUPPLY("PGA L Power On", RK817_CODEC_AMIC_CFG0, 5, 1, NULL, 0),
133 SND_SOC_DAPM_SUPPLY("Mic Boost L1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
134 SND_SOC_DAPM_SUPPLY("Mic Boost L2", RK817_CODEC_AMIC_CFG0, 2, 0, NULL, 0),
138 SND_SOC_DAPM_SUPPLY("PGA R Power On", RK817_CODEC_AMIC_CFG0, 4, 1, NULL, 0),
139 SND_SOC_DAPM_SUPPLY("Mic Boost R1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
140 SND_SOC_DAPM_SUPPLY("Mic Boost R2", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
143 SND_SOC_DAPM_SUPPLY("DAC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 3, 0, NULL, 0),
144 SND_SOC_DAPM_SUPPLY("I2S RX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 2, 0, NULL, 0),
145 SND_SOC_DAPM_SUPPLY("DAC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 1, 0, NULL, 0),
146 SND_SOC_DAPM_SUPPLY("I2S RX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 0, 0, NULL, 0),
147 SND_SOC_DAPM_SUPPLY("DAC Bias", RK817_CODEC_ADAC_CFG1, 3, 1, NULL, 0),
148 SND_SOC_DAPM_SUPPLY("DAC Mute Off", RK817_CODEC_DDAC_MUTE_MIXCTL, 0, 1, NULL, 0),
151 SND_SOC_DAPM_SUPPLY("Class D Mode", RK817_CODEC_DDAC_MUTE_MIXCTL, 4, 0, NULL, 0),
152 SND_SOC_DAPM_SUPPLY("High Pass Filter", RK817_CODEC_DDAC_MUTE_MIXCTL, 7, 0, NULL, 0),
154 SND_SOC_DAPM_SUPPLY("Enable Class D", RK817_CODEC_ACLASSD_CFG1, 7, 0, NULL, 0),
155 SND_SOC_DAPM_SUPPLY("Disable Class D Mute Ramp", RK817_CODEC_ACLASSD_CFG1, 6, 1, NULL, 0),
156 SND_SOC_DAPM_SUPPLY("Class D Mute Rate 1", RK817_CODEC_ACLASSD_CFG1, 3, 0, NULL, 0),
157 SND_SOC_DAPM_SUPPLY("Class D Mute Rate 2", RK817_CODEC_ACLASSD_CFG1, 2, 1, NULL, 0),
158 SND_SOC_DAPM_SUPPLY("Class D OCPP 2", RK817_CODEC_ACLASSD_CFG2, 5, 0, NULL, 0),
159 SND_SOC_DAPM_SUPPLY("Class D OCPP 3", RK817_CODEC_ACLASSD_CFG2, 4, 0, NULL, 0),
160 SND_SOC_DAPM_SUPPLY("Class D OCPN 2", RK817_CODEC_ACLASSD_CFG2, 1, 0, NULL, 0),
161 SND_SOC_DAPM_SUPPLY("Class D OCPN 3", RK817_CODEC_ACLASSD_CFG2, 0, 0, NULL, 0),
164 SND_SOC_DAPM_SUPPLY("Headphone Charge Pump", RK817_CODEC_AHP_CP, 4, 0, NULL, 0),
165 SND_SOC_DAPM_SUPPLY("Headphone CP Discharge LDO", RK817_CODEC_AHP_CP, 3, 1, NULL, 0),
166 SND_SOC_DAPM_SUPPLY("Headphone OStage", RK817_CODEC_AHP_CFG0, 6, 1, NULL, 0),
167 SND_SOC_DAPM_SUPPLY("Headphone Pre Amp", RK817_CODEC_AHP_CFG0, 5, 1, NULL, 0),
186 {"ADC L", NULL, "LDO Regulator"},
187 {"ADC L", NULL, "IBIAS Block"},
188 {"ADC L", NULL, "VAvg Buffer"},
189 {"ADC L", NULL, "PLL Power"},
190 {"ADC L", NULL, "ADC Clock"},
191 {"ADC L", NULL, "I2S TX Clock"},
192 {"ADC L", NULL, "ADC Channel Enable"},
193 {"ADC L", NULL, "I2S TX Channel Enable"},
194 {"ADC L", NULL, "I2S TX1 Transfer Start"},
195 {"MICL", NULL, "MIC Power On"},
196 {"MICL", NULL, "PGA L Power On"},
197 {"MICL", NULL, "Mic Boost L1"},
198 {"MICL", NULL, "Mic Boost L2"},
199 {"MICL", NULL, "I2S TX3 Transfer Start"},
200 {"MICL", NULL, "I2S TX3 Right Justified"},
201 {"ADC L", NULL, "MICL"},
204 {"ADC R", NULL, "LDO Regulator"},
205 {"ADC R", NULL, "IBIAS Block"},
206 {"ADC R", NULL, "VAvg Buffer"},
207 {"ADC R", NULL, "PLL Power"},
208 {"ADC R", NULL, "ADC Clock"},
209 {"ADC R", NULL, "I2S TX Clock"},
210 {"ADC R", NULL, "ADC Channel Enable"},
211 {"ADC R", NULL, "I2S TX Channel Enable"},
212 {"ADC R", NULL, "I2S TX1 Transfer Start"},
213 {"MICR", NULL, "MIC Power On"},
214 {"MICR", NULL, "PGA R Power On"},
215 {"MICR", NULL, "Mic Boost R1"},
216 {"MICR", NULL, "Mic Boost R2"},
217 {"MICR", NULL, "I2S TX3 Transfer Start"},
218 {"MICR", NULL, "I2S TX3 Right Justified"},
219 {"ADC R", NULL, "MICR"},
223 {"SPK DAC", NULL, "LDO Regulator"},
224 {"SPK DAC", NULL, "IBIAS Block"},
225 {"SPK DAC", NULL, "VAvg Buffer"},
226 {"SPK DAC", NULL, "PLL Power"},
227 {"SPK DAC", NULL, "I2S TX1 Transfer Start"},
228 {"SPK DAC", NULL, "DAC Clock"},
229 {"SPK DAC", NULL, "I2S RX Clock"},
230 {"SPK DAC", NULL, "DAC Channel Enable"},
231 {"SPK DAC", NULL, "I2S RX Channel Enable"},
232 {"SPK DAC", NULL, "Class D Mode"},
233 {"SPK DAC", NULL, "DAC Bias"},
234 {"SPK DAC", NULL, "DAC Mute Off"},
235 {"SPK DAC", NULL, "Enable Class D"},
236 {"SPK DAC", NULL, "Disable Class D Mute Ramp"},
237 {"SPK DAC", NULL, "Class D Mute Rate 1"},
238 {"SPK DAC", NULL, "Class D Mute Rate 2"},
239 {"SPK DAC", NULL, "Class D OCPP 2"},
240 {"SPK DAC", NULL, "Class D OCPP 3"},
241 {"SPK DAC", NULL, "Class D OCPN 2"},
242 {"SPK DAC", NULL, "Class D OCPN 3"},
243 {"SPK DAC", NULL, "High Pass Filter"},
246 {"DAC L", NULL, "LDO Regulator"},
247 {"DAC L", NULL, "IBIAS Block"},
248 {"DAC L", NULL, "VAvg Buffer"},
249 {"DAC L", NULL, "PLL Power"},
250 {"DAC L", NULL, "I2S TX1 Transfer Start"},
251 {"DAC L", NULL, "DAC Clock"},
252 {"DAC L", NULL, "I2S RX Clock"},
253 {"DAC L", NULL, "DAC Channel Enable"},
254 {"DAC L", NULL, "I2S RX Channel Enable"},
255 {"DAC L", NULL, "DAC Bias"},
256 {"DAC L", NULL, "DAC Mute Off"},
257 {"DAC L", NULL, "Headphone Charge Pump"},
258 {"DAC L", NULL, "Headphone CP Discharge LDO"},
259 {"DAC L", NULL, "Headphone OStage"},
260 {"DAC L", NULL, "Headphone Pre Amp"},
263 {"DAC R", NULL, "LDO Regulator"},
264 {"DAC R", NULL, "IBIAS Block"},
265 {"DAC R", NULL, "VAvg Buffer"},
266 {"DAC R", NULL, "PLL Power"},
267 {"DAC R", NULL, "I2S TX1 Transfer Start"},
268 {"DAC R", NULL, "DAC Clock"},
269 {"DAC R", NULL, "I2S RX Clock"},
270 {"DAC R", NULL, "DAC Channel Enable"},
271 {"DAC R", NULL, "I2S RX Channel Enable"},
272 {"DAC R", NULL, "DAC Bias"},
273 {"DAC R", NULL, "DAC Mute Off"},
274 {"DAC R", NULL, "Headphone Charge Pump"},
275 {"DAC R", NULL, "Headphone CP Discharge LDO"},
276 {"DAC R", NULL, "Headphone OStage"},
277 {"DAC R", NULL, "Headphone Pre Amp"},
283 {"SPKO", NULL, "Playback Mux"},
284 {"HPOL", NULL, "Playback Mux"},
285 {"HPOR", NULL, "Playback Mux"},