Lines Matching full:wsa
20 #include "lpass-wsa-macro.h"
614 SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
617 SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
620 /* WSA Macro */
885 struct wsa_macro *wsa = dev_get_drvdata(dev); in wsa_is_rw_register() local
991 if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5) in wsa_is_rw_register()
1030 struct wsa_macro *wsa = dev_get_drvdata(dev); in wsa_is_readable_register() local
1052 if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5) in wsa_is_readable_register()
1080 struct wsa_macro *wsa = dev_get_drvdata(dev); in wsa_is_volatile_register() local
1100 if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5) in wsa_is_volatile_register()
1130 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_set_spkr_mode() local
1132 wsa->spkr_mode = mode; in wsa_macro_set_spkr_mode()
1166 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_set_prim_interpolator_rate() local
1168 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { in wsa_macro_set_prim_interpolator_rate()
1186 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1188 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1190 wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1218 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_set_mix_interpolator_rate() local
1220 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { in wsa_macro_set_mix_interpolator_rate()
1231 wsa->reg_layout->rx_intx_2_sel_mask); in wsa_macro_set_mix_interpolator_rate()
1288 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_hw_params() local
1303 wsa->pcm_rate_vi = params_rate(params); in wsa_macro_hw_params()
1317 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_get_channel_map() local
1322 *tx_slot = wsa->active_ch_mask[dai->id]; in wsa_macro_get_channel_map()
1323 *tx_num = wsa->active_ch_cnt[dai->id]; in wsa_macro_get_channel_map()
1327 for_each_set_bit(temp, &wsa->active_ch_mask[dai->id], in wsa_macro_get_channel_map()
1422 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) in wsa_macro_mclk_enable() argument
1424 struct regmap *regmap = wsa->regmap; in wsa_macro_mclk_enable()
1427 if (wsa->wsa_mclk_users == 0) { in wsa_macro_mclk_enable()
1441 wsa->wsa_mclk_users++; in wsa_macro_mclk_enable()
1443 if (wsa->wsa_mclk_users <= 0) { in wsa_macro_mclk_enable()
1444 dev_err(wsa->dev, "clock already disabled\n"); in wsa_macro_mclk_enable()
1445 wsa->wsa_mclk_users = 0; in wsa_macro_mclk_enable()
1448 wsa->wsa_mclk_users--; in wsa_macro_mclk_enable()
1449 if (wsa->wsa_mclk_users == 0) { in wsa_macro_mclk_enable()
1510 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_enable_disable_vi_feedback() local
1512 if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) in wsa_macro_enable_disable_vi_feedback()
1517 if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) in wsa_macro_enable_disable_vi_feedback()
1527 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_mclk_event() local
1529 wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU); in wsa_macro_mclk_event()
1538 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_enable_vi_feedback() local
1541 switch (wsa->pcm_rate_vi) { in wsa_macro_enable_vi_feedback()
1654 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_config_compander() local
1656 if (!wsa->comp_enabled[comp]) in wsa_macro_config_compander()
1660 (comp * wsa->reg_layout->compander1_reg_offset); in wsa_macro_config_compander()
1702 struct wsa_macro *wsa, in wsa_macro_enable_softclip_clk() argument
1706 u16 softclip_clk_reg = wsa->reg_layout->softclip0_reg_base + in wsa_macro_enable_softclip_clk()
1707 (path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_enable_softclip_clk()
1712 if (wsa->softclip_clk_users[path] == 0) { in wsa_macro_enable_softclip_clk()
1721 wsa->softclip_clk_users[path]++; in wsa_macro_enable_softclip_clk()
1723 wsa->softclip_clk_users[path]--; in wsa_macro_enable_softclip_clk()
1724 if (wsa->softclip_clk_users[path] == 0) { in wsa_macro_enable_softclip_clk()
1740 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_config_softclip() local
1748 if (!wsa->is_softclip_on[softclip_path]) in wsa_macro_config_softclip()
1752 (softclip_path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_config_softclip()
1756 wsa_macro_enable_softclip_clk(component, wsa, softclip_path, in wsa_macro_config_softclip()
1767 wsa_macro_enable_softclip_clk(component, wsa, softclip_path, in wsa_macro_config_softclip()
1777 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_adie_lb() local
1785 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_adie_lb()
1791 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask); in wsa_macro_adie_lb()
1797 wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask); in wsa_macro_adie_lb()
1852 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_enable_prim_interpolator() local
1858 wsa->prim_int_users[ind]++; in wsa_macro_enable_prim_interpolator()
1859 if (wsa->prim_int_users[ind] == 1) { in wsa_macro_enable_prim_interpolator()
1880 wsa->prim_int_users[ind]--; in wsa_macro_enable_prim_interpolator()
1881 if (wsa->prim_int_users[ind] == 0) { in wsa_macro_enable_prim_interpolator()
1894 struct wsa_macro *wsa, in wsa_macro_config_ear_spkr_gain() argument
1899 switch (wsa->spkr_mode) { in wsa_macro_config_ear_spkr_gain()
1913 if (wsa->comp_enabled[WSA_MACRO_COMP1] && in wsa_macro_config_ear_spkr_gain()
1915 (wsa->ear_spkr_gain != 0)) { in wsa_macro_config_ear_spkr_gain()
1917 val = comp_gain_offset + wsa->ear_spkr_gain - 1; in wsa_macro_config_ear_spkr_gain()
1926 if (wsa->comp_enabled[WSA_MACRO_COMP1] && in wsa_macro_config_ear_spkr_gain()
1928 (wsa->ear_spkr_gain != 0)) { in wsa_macro_config_ear_spkr_gain()
1945 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_enable_interpolator() local
1964 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && in wsa_macro_enable_interpolator()
1965 (wsa->comp_enabled[WSA_MACRO_COMP1] || in wsa_macro_enable_interpolator()
1966 wsa->comp_enabled[WSA_MACRO_COMP2])) { in wsa_macro_enable_interpolator()
1986 wsa_macro_config_ear_spkr_gain(component, wsa, in wsa_macro_enable_interpolator()
1993 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && in wsa_macro_enable_interpolator()
1994 (wsa->comp_enabled[WSA_MACRO_COMP1] || in wsa_macro_enable_interpolator()
1995 wsa->comp_enabled[WSA_MACRO_COMP2])) { in wsa_macro_enable_interpolator()
2013 wsa_macro_config_ear_spkr_gain(component, wsa, in wsa_macro_enable_interpolator()
2077 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_enable_echo() local
2097 if (wsa->ec_hq[ec_tx]) { in wsa_macro_enable_echo()
2118 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_get_ec_hq() local
2120 ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx]; in wsa_macro_get_ec_hq()
2131 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_set_ec_hq() local
2133 wsa->ec_hq[ec_tx] = value; in wsa_macro_set_ec_hq()
2144 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_get_compander() local
2146 ucontrol->value.integer.value[0] = wsa->comp_enabled[comp]; in wsa_macro_get_compander()
2156 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_set_compander() local
2158 wsa->comp_enabled[comp] = value; in wsa_macro_set_compander()
2167 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_ear_spkr_pa_gain_get() local
2169 ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; in wsa_macro_ear_spkr_pa_gain_get()
2178 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_ear_spkr_pa_gain_put() local
2180 wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; in wsa_macro_ear_spkr_pa_gain_put()
2192 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_rx_mux_get() local
2195 wsa->rx_port_value[widget->shift]; in wsa_macro_rx_mux_get()
2211 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_rx_mux_put() local
2213 aif_rst = wsa->rx_port_value[widget->shift]; in wsa_macro_rx_mux_put()
2222 wsa->rx_port_value[widget->shift] = rx_port_value; in wsa_macro_rx_mux_put()
2228 if (wsa->active_ch_cnt[aif_rst]) { in wsa_macro_rx_mux_put()
2230 &wsa->active_ch_mask[aif_rst]); in wsa_macro_rx_mux_put()
2231 wsa->active_ch_cnt[aif_rst]--; in wsa_macro_rx_mux_put()
2237 &wsa->active_ch_mask[rx_port_value]); in wsa_macro_rx_mux_put()
2238 wsa->active_ch_cnt[rx_port_value]++; in wsa_macro_rx_mux_put()
2242 "%s: Invalid AIF_ID for WSA RX MUX %d\n", in wsa_macro_rx_mux_put()
2256 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_soft_clip_enable_get() local
2259 ucontrol->value.integer.value[0] = wsa->is_softclip_on[path]; in wsa_macro_soft_clip_enable_get()
2268 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_soft_clip_enable_put() local
2271 wsa->is_softclip_on[path] = ucontrol->value.integer.value[0]; in wsa_macro_soft_clip_enable_put()
2314 SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
2316 SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
2318 SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
2320 SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
2330 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_vi_feed_mixer_get() local
2334 if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id])) in wsa_macro_vi_feed_mixer_get()
2348 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); in wsa_macro_vi_feed_mixer_put() local
2356 &wsa->active_ch_mask[dai_id])) { in wsa_macro_vi_feed_mixer_put()
2358 &wsa->active_ch_mask[dai_id]); in wsa_macro_vi_feed_mixer_put()
2359 wsa->active_ch_cnt[dai_id]++; in wsa_macro_vi_feed_mixer_put()
2363 &wsa->active_ch_mask[dai_id])) { in wsa_macro_vi_feed_mixer_put()
2365 &wsa->active_ch_mask[dai_id]); in wsa_macro_vi_feed_mixer_put()
2366 wsa->active_ch_cnt[dai_id]++; in wsa_macro_vi_feed_mixer_put()
2371 &wsa->active_ch_mask[dai_id])) { in wsa_macro_vi_feed_mixer_put()
2373 &wsa->active_ch_mask[dai_id]); in wsa_macro_vi_feed_mixer_put()
2374 wsa->active_ch_cnt[dai_id]--; in wsa_macro_vi_feed_mixer_put()
2378 &wsa->active_ch_mask[dai_id])) { in wsa_macro_vi_feed_mixer_put()
2380 &wsa->active_ch_mask[dai_id]); in wsa_macro_vi_feed_mixer_put()
2381 wsa->active_ch_cnt[dai_id]--; in wsa_macro_vi_feed_mixer_put()
2399 SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
2401 SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
2404 SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
2408 SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
2413 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
2417 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
2422 SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
2424 SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
2426 SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
2428 SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
2431 SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2432 SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2433 SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2434 SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2447 SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
2520 {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
2521 {"WSA AIF_VI", NULL, "WSA_MCLK"},
2523 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2524 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2525 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2526 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2527 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
2528 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
2529 {"WSA AIF_ECHO", NULL, "WSA_MCLK"},
2531 {"WSA AIF1 PB", NULL, "WSA_MCLK"},
2532 {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},
2534 {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2535 {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2536 {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2537 {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2539 {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2540 {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2541 {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2542 {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2544 {"WSA RX0", NULL, "WSA RX0 MUX"},
2545 {"WSA RX1", NULL, "WSA RX1 MUX"},
2546 {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
2547 {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},
2549 {"WSA RX0", NULL, "WSA_RX0_CLK"},
2550 {"WSA RX1", NULL, "WSA_RX1_CLK"},
2551 {"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"},
2552 {"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"},
2554 {"WSA_RX0 INP0", "RX0", "WSA RX0"},
2555 {"WSA_RX0 INP0", "RX1", "WSA RX1"},
2556 {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
2557 {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
2562 {"WSA_RX0 INP1", "RX0", "WSA RX0"},
2563 {"WSA_RX0 INP1", "RX1", "WSA RX1"},
2564 {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
2565 {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
2570 {"WSA_RX0 INP2", "RX0", "WSA RX0"},
2571 {"WSA_RX0 INP2", "RX1", "WSA RX1"},
2572 {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
2573 {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
2578 {"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
2579 {"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
2580 {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2581 {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2586 {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
2593 {"WSA_RX1 INP0", "RX0", "WSA RX0"},
2594 {"WSA_RX1 INP0", "RX1", "WSA RX1"},
2595 {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
2596 {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
2601 {"WSA_RX1 INP1", "RX0", "WSA RX0"},
2602 {"WSA_RX1 INP1", "RX1", "WSA RX1"},
2603 {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
2604 {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
2609 {"WSA_RX1 INP2", "RX0", "WSA RX0"},
2610 {"WSA_RX1 INP2", "RX1", "WSA RX1"},
2611 {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
2612 {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
2617 {"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
2618 {"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
2619 {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2620 {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2631 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) in wsa_swrm_clock() argument
2633 struct regmap *regmap = wsa->regmap; in wsa_swrm_clock()
2638 ret = clk_prepare_enable(wsa->mclk); in wsa_swrm_clock()
2640 dev_err(wsa->dev, "failed to enable mclk\n"); in wsa_swrm_clock()
2643 wsa_macro_mclk_enable(wsa, true); in wsa_swrm_clock()
2652 wsa_macro_mclk_enable(wsa, false); in wsa_swrm_clock()
2653 clk_disable_unprepare(wsa->mclk); in wsa_swrm_clock()
2662 struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp); in wsa_macro_component_probe() local
2666 snd_soc_component_init_regmap(comp, wsa->regmap); in wsa_macro_component_probe()
2668 wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; in wsa_macro_component_probe()
2681 switch (wsa->codec_version) { in wsa_macro_component_probe()
2716 struct wsa_macro *wsa = to_wsa_macro(hw); in swclk_gate_is_enabled() local
2719 regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
2738 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa) in wsa_macro_register_mclk_output() argument
2740 struct device *dev = wsa->dev; in wsa_macro_register_mclk_output()
2746 if (wsa->npl) in wsa_macro_register_mclk_output()
2747 parent_clk_name = __clk_get_name(wsa->npl); in wsa_macro_register_mclk_output()
2749 parent_clk_name = __clk_get_name(wsa->mclk); in wsa_macro_register_mclk_output()
2758 wsa->hw.init = &init; in wsa_macro_register_mclk_output()
2759 hw = &wsa->hw; in wsa_macro_register_mclk_output()
2760 ret = clk_hw_register(wsa->dev, hw); in wsa_macro_register_mclk_output()
2768 .name = "WSA MACRO",
2781 struct wsa_macro *wsa; in wsa_macro_probe() local
2788 wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL); in wsa_macro_probe()
2789 if (!wsa) in wsa_macro_probe()
2792 wsa->macro = devm_clk_get_optional(dev, "macro"); in wsa_macro_probe()
2793 if (IS_ERR(wsa->macro)) in wsa_macro_probe()
2794 return dev_err_probe(dev, PTR_ERR(wsa->macro), "unable to get macro clock\n"); in wsa_macro_probe()
2796 wsa->dcodec = devm_clk_get_optional(dev, "dcodec"); in wsa_macro_probe()
2797 if (IS_ERR(wsa->dcodec)) in wsa_macro_probe()
2798 return dev_err_probe(dev, PTR_ERR(wsa->dcodec), "unable to get dcodec clock\n"); in wsa_macro_probe()
2800 wsa->mclk = devm_clk_get(dev, "mclk"); in wsa_macro_probe()
2801 if (IS_ERR(wsa->mclk)) in wsa_macro_probe()
2802 return dev_err_probe(dev, PTR_ERR(wsa->mclk), "unable to get mclk clock\n"); in wsa_macro_probe()
2805 wsa->npl = devm_clk_get(dev, "npl"); in wsa_macro_probe()
2806 if (IS_ERR(wsa->npl)) in wsa_macro_probe()
2807 return dev_err_probe(dev, PTR_ERR(wsa->npl), "unable to get npl clock\n"); in wsa_macro_probe()
2810 wsa->fsgen = devm_clk_get(dev, "fsgen"); in wsa_macro_probe()
2811 if (IS_ERR(wsa->fsgen)) in wsa_macro_probe()
2812 return dev_err_probe(dev, PTR_ERR(wsa->fsgen), "unable to get fsgen clock\n"); in wsa_macro_probe()
2818 wsa->codec_version = lpass_macro_get_codec_version(); in wsa_macro_probe()
2821 switch (wsa->codec_version) { in wsa_macro_probe()
2827 wsa->reg_layout = &wsa_codec_v2_1; in wsa_macro_probe()
2842 wsa->reg_layout = &wsa_codec_v2_5; in wsa_macro_probe()
2854 dev_err(dev, "Unsupported Codec version (%d)\n", wsa->codec_version); in wsa_macro_probe()
2867 wsa->regmap = devm_regmap_init_mmio(dev, base, reg_config); in wsa_macro_probe()
2868 if (IS_ERR(wsa->regmap)) in wsa_macro_probe()
2869 return PTR_ERR(wsa->regmap); in wsa_macro_probe()
2871 dev_set_drvdata(dev, wsa); in wsa_macro_probe()
2873 wsa->dev = dev; in wsa_macro_probe()
2876 clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ); in wsa_macro_probe()
2877 clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ); in wsa_macro_probe()
2879 ret = clk_prepare_enable(wsa->macro); in wsa_macro_probe()
2883 ret = clk_prepare_enable(wsa->dcodec); in wsa_macro_probe()
2887 ret = clk_prepare_enable(wsa->mclk); in wsa_macro_probe()
2891 ret = clk_prepare_enable(wsa->npl); in wsa_macro_probe()
2895 ret = clk_prepare_enable(wsa->fsgen); in wsa_macro_probe()
2900 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, in wsa_macro_probe()
2903 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, in wsa_macro_probe()
2907 regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, in wsa_macro_probe()
2922 ret = wsa_macro_register_mclk_output(wsa); in wsa_macro_probe()
2929 clk_disable_unprepare(wsa->fsgen); in wsa_macro_probe()
2931 clk_disable_unprepare(wsa->npl); in wsa_macro_probe()
2933 clk_disable_unprepare(wsa->mclk); in wsa_macro_probe()
2935 clk_disable_unprepare(wsa->dcodec); in wsa_macro_probe()
2937 clk_disable_unprepare(wsa->macro); in wsa_macro_probe()
2945 struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); in wsa_macro_remove() local
2947 clk_disable_unprepare(wsa->macro); in wsa_macro_remove()
2948 clk_disable_unprepare(wsa->dcodec); in wsa_macro_remove()
2949 clk_disable_unprepare(wsa->mclk); in wsa_macro_remove()
2950 clk_disable_unprepare(wsa->npl); in wsa_macro_remove()
2951 clk_disable_unprepare(wsa->fsgen); in wsa_macro_remove()
2956 struct wsa_macro *wsa = dev_get_drvdata(dev); in wsa_macro_runtime_suspend() local
2958 regcache_cache_only(wsa->regmap, true); in wsa_macro_runtime_suspend()
2959 regcache_mark_dirty(wsa->regmap); in wsa_macro_runtime_suspend()
2961 clk_disable_unprepare(wsa->fsgen); in wsa_macro_runtime_suspend()
2962 clk_disable_unprepare(wsa->npl); in wsa_macro_runtime_suspend()
2963 clk_disable_unprepare(wsa->mclk); in wsa_macro_runtime_suspend()
2970 struct wsa_macro *wsa = dev_get_drvdata(dev); in wsa_macro_runtime_resume() local
2973 ret = clk_prepare_enable(wsa->mclk); in wsa_macro_runtime_resume()
2979 ret = clk_prepare_enable(wsa->npl); in wsa_macro_runtime_resume()
2985 ret = clk_prepare_enable(wsa->fsgen); in wsa_macro_runtime_resume()
2991 regcache_cache_only(wsa->regmap, false); in wsa_macro_runtime_resume()
2992 regcache_sync(wsa->regmap); in wsa_macro_runtime_resume()
2996 clk_disable_unprepare(wsa->npl); in wsa_macro_runtime_resume()
2998 clk_disable_unprepare(wsa->mclk); in wsa_macro_runtime_resume()
3009 .compatible = "qcom,sc7280-lpass-wsa-macro",
3012 .compatible = "qcom,sm8250-lpass-wsa-macro",
3015 .compatible = "qcom,sm8450-lpass-wsa-macro",
3018 .compatible = "qcom,sm8550-lpass-wsa-macro",
3020 .compatible = "qcom,sc8280xp-lpass-wsa-macro",
3038 MODULE_DESCRIPTION("WSA macro driver");