Lines Matching +full:sm8250 +full:- +full:lpass +full:- +full:tx +full:- +full:macro
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
14 #include <sound/soc-dapm.h>
17 #include <linux/clk-provider.h>
19 #include "lpass-macro-common.h"
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n)
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n)
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n)
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n)
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n)
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n)
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n)
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n)
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n)
206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
269 /* LPASS CODEC version 2.5 rx reg offsets */
665 struct clk *macro; member
678 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
888 /* RX Macro */
1242 /* Update volatile list for rx/tx macros */ in rx_is_volatile_register()
1603 switch (rx->codec_version) { in rx_is_rw_register()
1685 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_int_dem_inp_mux_put()
1687 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_int_dem_inp_mux_put()
1691 val = ucontrol->value.enumerated.item[0]; in rx_macro_int_dem_inp_mux_put()
1693 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) in rx_macro_int_dem_inp_mux_put()
1695 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) in rx_macro_int_dem_inp_mux_put()
1730 struct snd_soc_component *component = dai->component; in rx_macro_set_prim_interpolator_rate()
1733 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1775 struct snd_soc_component *component = dai->component; in rx_macro_set_mix_interpolator_rate()
1778 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1821 struct snd_soc_component *component = dai->component; in rx_macro_hw_params()
1825 switch (substream->stream) { in rx_macro_hw_params()
1829 dev_err(component->dev, "%s: cannot set sample rate: %u\n", in rx_macro_hw_params()
1833 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1845 struct snd_soc_component *component = dai->component; in rx_macro_get_channel_map()
1849 switch (dai->id) { in rx_macro_get_channel_map()
1854 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1861 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1862 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1863 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 in rx_macro_get_channel_map()
1864 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 in rx_macro_get_channel_map()
1875 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1897 dev_err(component->dev, "%s: Invalid AIF\n", __func__); in rx_macro_get_channel_map()
1905 struct snd_soc_component *component = dai->component; in rx_macro_digital_mute()
1911 switch (dai->id) { in rx_macro_digital_mute()
2038 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
2041 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2055 rx->rx_mclk_users++; in rx_macro_mclk_enable()
2057 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
2058 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
2059 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
2062 rx->rx_mclk_users--; in rx_macro_mclk_enable()
2063 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2079 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_mclk_event()
2091 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); in rx_macro_mclk_event()
2092 ret = -EINVAL; in rx_macro_mclk_event()
2140 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_main_path()
2144 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); in rx_macro_enable_main_path()
2145 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); in rx_macro_enable_main_path()
2149 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2150 if (rx_macro_adie_lb(component, w->shift)) in rx_macro_enable_main_path()
2160 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2194 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2235 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2249 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2268 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2271 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2273 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2274 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2284 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2309 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2325 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2326 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2328 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2329 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2357 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2373 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2438 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_get_compander()
2441 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2449 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_set_compander()
2450 int value = ucontrol->value.integer.value[0]; in rx_macro_set_compander()
2453 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2462 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_get()
2465 ucontrol->value.enumerated.item[0] = in rx_macro_mux_get()
2466 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2474 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_put()
2475 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_mux_put()
2477 u32 rx_port_value = ucontrol->value.enumerated.item[0]; in rx_macro_mux_put()
2481 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2486 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); in rx_macro_mux_put()
2490 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2494 if (rx->active_ch_cnt[aif_rst]) { in rx_macro_mux_put()
2495 clear_bit(widget->shift, in rx_macro_mux_put()
2496 &rx->active_ch_mask[aif_rst]); in rx_macro_mux_put()
2497 rx->active_ch_cnt[aif_rst]--; in rx_macro_mux_put()
2504 set_bit(widget->shift, in rx_macro_mux_put()
2505 &rx->active_ch_mask[rx_port_value]); in rx_macro_mux_put()
2506 rx->active_ch_cnt[rx_port_value]++; in rx_macro_mux_put()
2509 dev_err(component->dev, in rx_macro_mux_put()
2515 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, in rx_macro_mux_put()
2519 return -EINVAL; in rx_macro_mux_put()
2547 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2557 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2567 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2577 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2587 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2597 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2607 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2618 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2629 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2640 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2662 return -EINVAL; in rx_macro_hphdelay_lutbypass()
2667 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2679 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2708 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2717 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2727 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2731 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2732 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2733 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2760 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2765 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2771 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_mix_path()
2775 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2776 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2780 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2790 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2806 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_rx_path_clk()
2811 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2812 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2814 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), in rx_macro_enable_rx_path_clk()
2818 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2820 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2831 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_set_iir_gain()
2836 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { in rx_macro_set_iir_gain()
2918 /* Mask top 2 bits, 7-8 are reserved */ in set_iir_band_coeff()
2929 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_put_iir_band_audio_mixer()
2930 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_put_iir_band_audio_mixer()
2931 int iir_idx = ctl->iir_idx; in rx_macro_put_iir_band_audio_mixer()
2932 int band_idx = ctl->band_idx; in rx_macro_put_iir_band_audio_mixer()
2936 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); in rx_macro_put_iir_band_audio_mixer()
2958 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_get_iir_band_audio_mixer()
2959 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_get_iir_band_audio_mixer()
2960 int iir_idx = ctl->iir_idx; in rx_macro_get_iir_band_audio_mixer()
2961 int band_idx = ctl->band_idx; in rx_macro_get_iir_band_audio_mixer()
2970 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); in rx_macro_get_iir_band_audio_mixer()
2979 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_iir_filter_info()
2980 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_iir_filter_info()
2982 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in rx_macro_iir_filter_info()
2983 ucontrol->count = params->max; in rx_macro_iir_filter_info()
2990 -84, 40, digital_gain),
2992 -84, 40, digital_gain),
2994 -84, 40, digital_gain),
2996 -84, 40, digital_gain),
3002 -84, 40, digital_gain),
3004 -84, 40, digital_gain),
3006 -84, 40, digital_gain),
3008 -84, 40, digital_gain),
3013 -84, 40, digital_gain),
3015 -84, 40, digital_gain),
3038 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3041 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3044 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3047 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3050 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3053 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3056 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3059 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3101 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_echo()
3103 int ec_tx = -1; in rx_macro_enable_echo()
3108 ec_tx = ((val & 0xf0) >> 0x4) - 1; in rx_macro_enable_echo()
3110 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3115 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3118 dev_err(component->dev, "%s: EC mix control not set correctly\n", in rx_macro_enable_echo()
3120 return -EINVAL; in rx_macro_enable_echo()
3615 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3636 switch (rx->codec_version) { in rx_macro_component_probe()
3657 return -EINVAL; in rx_macro_component_probe()
3660 rx->component = component; in rx_macro_component_probe()
3674 ret = clk_prepare_enable(rx->mclk); in swclk_gate_enable()
3676 dev_err(rx->dev, "unable to prepare mclk\n"); in swclk_gate_enable()
3682 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3692 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3696 clk_disable_unprepare(rx->mclk); in swclk_gate_disable()
3704 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3726 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3728 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3733 if (rx->npl) in rx_macro_register_mclk_output()
3734 parent_clk_name = __clk_get_name(rx->npl); in rx_macro_register_mclk_output()
3736 parent_clk_name = __clk_get_name(rx->mclk); in rx_macro_register_mclk_output()
3743 rx->hw.init = &init; in rx_macro_register_mclk_output()
3744 hw = &rx->hw; in rx_macro_register_mclk_output()
3745 ret = devm_clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3753 .name = "RX-MACRO",
3765 struct device *dev = &pdev->dev; in rx_macro_probe()
3775 return -ENOMEM; in rx_macro_probe()
3777 rx->macro = devm_clk_get_optional(dev, "macro"); in rx_macro_probe()
3778 if (IS_ERR(rx->macro)) in rx_macro_probe()
3779 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); in rx_macro_probe()
3781 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); in rx_macro_probe()
3782 if (IS_ERR(rx->dcodec)) in rx_macro_probe()
3783 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); in rx_macro_probe()
3785 rx->mclk = devm_clk_get(dev, "mclk"); in rx_macro_probe()
3786 if (IS_ERR(rx->mclk)) in rx_macro_probe()
3787 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); in rx_macro_probe()
3790 rx->npl = devm_clk_get(dev, "npl"); in rx_macro_probe()
3791 if (IS_ERR(rx->npl)) in rx_macro_probe()
3792 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); in rx_macro_probe()
3795 rx->fsgen = devm_clk_get(dev, "fsgen"); in rx_macro_probe()
3796 if (IS_ERR(rx->fsgen)) in rx_macro_probe()
3797 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); in rx_macro_probe()
3799 rx->pds = lpass_macro_pds_init(dev); in rx_macro_probe()
3800 if (IS_ERR(rx->pds)) in rx_macro_probe()
3801 return PTR_ERR(rx->pds); in rx_macro_probe()
3803 ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds); in rx_macro_probe()
3811 rx->codec_version = lpass_macro_get_codec_version(); in rx_macro_probe()
3814 switch (rx->codec_version) { in rx_macro_probe()
3820 rx->rxn_reg_stride = 0x80; in rx_macro_probe()
3821 rx->rxn_reg_stride2 = 0xc; in rx_macro_probe()
3825 return -ENOMEM; in rx_macro_probe()
3834 rx->rxn_reg_stride = 0xc0; in rx_macro_probe()
3835 rx->rxn_reg_stride2 = 0x0; in rx_macro_probe()
3839 return -ENOMEM; in rx_macro_probe()
3845 dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version); in rx_macro_probe()
3846 return -EINVAL; in rx_macro_probe()
3853 return -ENOMEM; in rx_macro_probe()
3855 reg_config->reg_defaults = reg_defaults; in rx_macro_probe()
3856 reg_config->num_reg_defaults = def_count; in rx_macro_probe()
3858 rx->regmap = devm_regmap_init_mmio(dev, base, reg_config); in rx_macro_probe()
3859 if (IS_ERR(rx->regmap)) in rx_macro_probe()
3860 return PTR_ERR(rx->regmap); in rx_macro_probe()
3864 rx->dev = dev; in rx_macro_probe()
3867 clk_set_rate(rx->mclk, MCLK_FREQ); in rx_macro_probe()
3868 clk_set_rate(rx->npl, MCLK_FREQ); in rx_macro_probe()
3870 ret = clk_prepare_enable(rx->macro); in rx_macro_probe()
3874 ret = clk_prepare_enable(rx->dcodec); in rx_macro_probe()
3878 ret = clk_prepare_enable(rx->mclk); in rx_macro_probe()
3882 ret = clk_prepare_enable(rx->npl); in rx_macro_probe()
3886 ret = clk_prepare_enable(rx->fsgen); in rx_macro_probe()
3891 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3895 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3898 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3921 clk_disable_unprepare(rx->fsgen); in rx_macro_probe()
3923 clk_disable_unprepare(rx->npl); in rx_macro_probe()
3925 clk_disable_unprepare(rx->mclk); in rx_macro_probe()
3927 clk_disable_unprepare(rx->dcodec); in rx_macro_probe()
3929 clk_disable_unprepare(rx->macro); in rx_macro_probe()
3936 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove()
3938 clk_disable_unprepare(rx->mclk); in rx_macro_remove()
3939 clk_disable_unprepare(rx->npl); in rx_macro_remove()
3940 clk_disable_unprepare(rx->fsgen); in rx_macro_remove()
3941 clk_disable_unprepare(rx->macro); in rx_macro_remove()
3942 clk_disable_unprepare(rx->dcodec); in rx_macro_remove()
3947 .compatible = "qcom,sc7280-lpass-rx-macro",
3951 .compatible = "qcom,sm8250-lpass-rx-macro",
3954 .compatible = "qcom,sm8450-lpass-rx-macro",
3957 .compatible = "qcom,sm8550-lpass-rx-macro",
3959 .compatible = "qcom,sc8280xp-lpass-rx-macro",
3970 regcache_cache_only(rx->regmap, true); in rx_macro_runtime_suspend()
3971 regcache_mark_dirty(rx->regmap); in rx_macro_runtime_suspend()
3973 clk_disable_unprepare(rx->fsgen); in rx_macro_runtime_suspend()
3974 clk_disable_unprepare(rx->npl); in rx_macro_runtime_suspend()
3975 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_suspend()
3985 ret = clk_prepare_enable(rx->mclk); in rx_macro_runtime_resume()
3991 ret = clk_prepare_enable(rx->npl); in rx_macro_runtime_resume()
3997 ret = clk_prepare_enable(rx->fsgen); in rx_macro_runtime_resume()
4002 regcache_cache_only(rx->regmap, false); in rx_macro_runtime_resume()
4003 regcache_sync(rx->regmap); in rx_macro_runtime_resume()
4007 clk_disable_unprepare(rx->npl); in rx_macro_runtime_resume()
4009 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_resume()
4031 MODULE_DESCRIPTION("RX macro driver");