Lines Matching +full:0 +full:x070000
17 #define CS43130_FIRSTREG 0x010000
18 #define CS43130_LASTREG 0x190000
19 #define CS43130_CHIP_ID 0x00043130
20 #define CS4399_CHIP_ID 0x00043990
21 #define CS43131_CHIP_ID 0x00043131
22 #define CS43198_CHIP_ID 0x00043198
23 #define CS43130_DEVID_AB 0x010000 /* Device ID A & B [RO] */
24 #define CS43130_DEVID_CD 0x010001 /* Device ID C & D [RO] */
25 #define CS43130_DEVID_E 0x010002 /* Device ID E [RO] */
26 #define CS43130_FAB_ID 0x010003 /* Fab ID [RO] */
27 #define CS43130_REV_ID 0x010004 /* Revision ID [RO] */
28 #define CS43130_SUBREV_ID 0x010005 /* Subrevision ID */
29 #define CS43130_SYS_CLK_CTL_1 0x010006 /* System Clocking Ctl 1 */
30 #define CS43130_SP_SRATE 0x01000B /* Serial Port Sample Rate */
31 #define CS43130_SP_BITSIZE 0x01000C /* Serial Port Bit Size */
32 #define CS43130_PAD_INT_CFG 0x01000D /* Pad Interface Config */
33 #define CS43130_DXD1 0x010010 /* DXD1 */
34 #define CS43130_DXD7 0x010025 /* DXD7 */
35 #define CS43130_DXD19 0x010026 /* DXD19 */
36 #define CS43130_DXD17 0x010027 /* DXD17 */
37 #define CS43130_DXD18 0x010028 /* DXD18 */
38 #define CS43130_DXD12 0x01002C /* DXD12 */
39 #define CS43130_DXD8 0x01002E /* DXD8 */
40 #define CS43130_PWDN_CTL 0x020000 /* Power Down Ctl */
41 #define CS43130_DXD2 0x020019 /* DXD2 */
42 #define CS43130_CRYSTAL_SET 0x020052 /* Crystal Setting */
43 #define CS43130_PLL_SET_1 0x030001 /* PLL Setting 1 */
44 #define CS43130_PLL_SET_2 0x030002 /* PLL Setting 2 */
45 #define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */
46 #define CS43130_PLL_SET_4 0x030004 /* PLL Setting 4 */
47 #define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */
48 #define CS43130_PLL_SET_6 0x030008 /* PLL Setting 6 */
49 #define CS43130_PLL_SET_7 0x03000A /* PLL Setting 7 */
50 #define CS43130_PLL_SET_8 0x03001B /* PLL Setting 8 */
51 #define CS43130_PLL_SET_9 0x040002 /* PLL Setting 9 */
52 #define CS43130_PLL_SET_10 0x040003 /* PLL Setting 10 */
53 #define CS43130_CLKOUT_CTL 0x040004 /* CLKOUT Ctl */
54 #define CS43130_ASP_NUM_1 0x040010 /* ASP Numerator 1 */
55 #define CS43130_ASP_NUM_2 0x040011 /* ASP Numerator 2 */
56 #define CS43130_ASP_DEN_1 0x040012 /* ASP Denominator 1 */
57 #define CS43130_ASP_DEN_2 0x040013 /* ASP Denominator 2 */
58 #define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */
59 #define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */
60 #define CS43130_ASP_LRCK_PERIOD_1 0x040016 /* ASP LRCK Period 1 */
61 #define CS43130_ASP_LRCK_PERIOD_2 0x040017 /* ASP LRCK Period 2 */
62 #define CS43130_ASP_CLOCK_CONF 0x040018 /* ASP Clock Config */
63 #define CS43130_ASP_FRAME_CONF 0x040019 /* ASP Frame Config */
64 #define CS43130_XSP_NUM_1 0x040020 /* XSP Numerator 1 */
65 #define CS43130_XSP_NUM_2 0x040021 /* XSP Numerator 2 */
66 #define CS43130_XSP_DEN_1 0x040022 /* XSP Denominator 1 */
67 #define CS43130_XSP_DEN_2 0x040023 /* XSP Denominator 2 */
68 #define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */
69 #define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */
70 #define CS43130_XSP_LRCK_PERIOD_1 0x040026 /* XSP LRCK Period 1 */
71 #define CS43130_XSP_LRCK_PERIOD_2 0x040027 /* XSP LRCK Period 2 */
72 #define CS43130_XSP_CLOCK_CONF 0x040028 /* XSP Clock Config */
73 #define CS43130_XSP_FRAME_CONF 0x040029 /* XSP Frame Config */
74 #define CS43130_ASP_CH_1_LOC 0x050000 /* ASP Chan 1 Location */
75 #define CS43130_ASP_CH_2_LOC 0x050001 /* ASP Chan 2 Location */
76 #define CS43130_ASP_CH_1_SZ_EN 0x05000A /* ASP Chan 1 Size, Enable */
77 #define CS43130_ASP_CH_2_SZ_EN 0x05000B /* ASP Chan 2 Size, Enable */
78 #define CS43130_XSP_CH_1_LOC 0x060000 /* XSP Chan 1 Location */
79 #define CS43130_XSP_CH_2_LOC 0x060001 /* XSP Chan 2 Location */
80 #define CS43130_XSP_CH_1_SZ_EN 0x06000A /* XSP Chan 1 Size, Enable */
81 #define CS43130_XSP_CH_2_SZ_EN 0x06000B /* XSP Chan 2 Size, Enable */
82 #define CS43130_DSD_VOL_B 0x070000 /* DSD Volume B */
83 #define CS43130_DSD_VOL_A 0x070001 /* DSD Volume A */
84 #define CS43130_DSD_PATH_CTL_1 0x070002 /* DSD Proc Path Sig Ctl 1 */
85 #define CS43130_DSD_INT_CFG 0x070003 /* DSD Interface Config */
86 #define CS43130_DSD_PATH_CTL_2 0x070004 /* DSD Proc Path Sig Ctl 2 */
87 #define CS43130_DSD_PCM_MIX_CTL 0x070005 /* DSD and PCM Mixing Ctl */
88 #define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */
89 #define CS43130_HP_OUT_CTL_1 0x080000 /* HP Output Ctl 1 */
90 #define CS43130_DXD16 0x080024 /* DXD16 */
91 #define CS43130_DXD13 0x080032 /* DXD13 */
92 #define CS43130_PCM_FILT_OPT 0x090000 /* PCM Filter Option */
93 #define CS43130_PCM_VOL_B 0x090001 /* PCM Volume B */
94 #define CS43130_PCM_VOL_A 0x090002 /* PCM Volume A */
95 #define CS43130_PCM_PATH_CTL_1 0x090003 /* PCM Path Signal Ctl 1 */
96 #define CS43130_PCM_PATH_CTL_2 0x090004 /* PCM Path Signal Ctl 2 */
97 #define CS43130_DXD6 0x090097 /* DXD6 */
98 #define CS43130_CLASS_H_CTL 0x0B0000 /* Class H Ctl */
99 #define CS43130_DXD15 0x0B0005 /* DXD15 */
100 #define CS43130_DXD14 0x0B0006 /* DXD14 */
101 #define CS43130_DXD3 0x0C0002 /* DXD3 */
102 #define CS43130_DXD10 0x0C0003 /* DXD10 */
103 #define CS43130_DXD11 0x0C0005 /* DXD11 */
104 #define CS43130_DXD9 0x0C0006 /* DXD9 */
105 #define CS43130_DXD4 0x0C0009 /* DXD4 */
106 #define CS43130_DXD5 0x0C000E /* DXD5 */
107 #define CS43130_HP_DETECT 0x0D0000 /* HP Detect */
108 #define CS43130_HP_STATUS 0x0D0001 /* HP Status [RO] */
109 #define CS43130_HP_LOAD_1 0x0E0000 /* HP Load 1 */
110 #define CS43130_HP_MEAS_LOAD_1 0x0E0003 /* HP Load Measurement 1 */
111 #define CS43130_HP_MEAS_LOAD_2 0x0E0004 /* HP Load Measurement 2 */
112 #define CS43130_HP_DC_STAT_1 0x0E000D /* HP DC Load Status 0 [RO] */
113 #define CS43130_HP_DC_STAT_2 0x0E000E /* HP DC Load Status 1 [RO] */
114 #define CS43130_HP_AC_STAT_1 0x0E0010 /* HP AC Load Status 0 [RO] */
115 #define CS43130_HP_AC_STAT_2 0x0E0011 /* HP AC Load Status 1 [RO] */
116 #define CS43130_HP_LOAD_STAT 0x0E001A /* HP Load Status [RO] */
117 #define CS43130_INT_STATUS_1 0x0F0000 /* Interrupt Status 1 */
118 #define CS43130_INT_STATUS_2 0x0F0001 /* Interrupt Status 2 */
119 #define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */
120 #define CS43130_INT_STATUS_4 0x0F0003 /* Interrupt Status 4 */
121 #define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */
122 #define CS43130_INT_MASK_1 0x0F0010 /* Interrupt Mask 1 */
123 #define CS43130_INT_MASK_2 0x0F0011 /* Interrupt Mask 2 */
124 #define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */
125 #define CS43130_INT_MASK_4 0x0F0013 /* Interrupt Mask 4 */
126 #define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */
128 #define CS43130_MCLK_SRC_SEL_MASK 0x03
129 #define CS43130_MCLK_SRC_SEL_SHIFT 0
130 #define CS43130_MCLK_INT_MASK 0x04
132 #define CS43130_CH_BITSIZE_MASK 0x03
133 #define CS43130_CH_EN_MASK 0x04
135 #define CS43130_ASP_BITSIZE_MASK 0x03
136 #define CS43130_XSP_BITSIZE_MASK 0x0C
138 #define CS43130_SP_BITSIZE_ASP_SHIFT 0
140 #define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
150 #define CS43130_XTAL_RDY_INT_MASK 0x10
154 #define CS43130_PLL_RDY_INT_MASK 0x04
159 #define CS43130_INT_MASK_ALL 0xFF
184 #define CS43130_SP_BIT_SIZE_8 0x03
185 #define CS43130_SP_BIT_SIZE_16 0x02
186 #define CS43130_SP_BIT_SIZE_24 0x01
187 #define CS43130_SP_BIT_SIZE_32 0x00
190 #define CS43130_CH_BIT_SIZE_8 0x00
191 #define CS43130_CH_BIT_SIZE_16 0x01
192 #define CS43130_CH_BIT_SIZE_24 0x02
193 #define CS43130_CH_BIT_SIZE_32 0x03
196 #define CS43130_PLL_START_MASK 0x01
197 #define CS43130_PLL_MODE_MASK 0x02
200 #define CS43130_PLL_REF_PREDIV_MASK 0x3
202 #define CS43130_SP_STP_MASK 0x10
204 #define CS43130_SP_5050_MASK 0x08
206 #define CS43130_SP_FSD_MASK 0x07
208 #define CS43130_SP_MODE_MASK 0x10
210 #define CS43130_SP_SCPOL_OUT_MASK 0x08
212 #define CS43130_SP_SCPOL_IN_MASK 0x04
214 #define CS43130_SP_LCPOL_OUT_MASK 0x02
216 #define CS43130_SP_LCPOL_IN_MASK 0x01
217 #define CS43130_SP_LCPOL_IN_SHIFT 0
220 #define CS43130_PDN_XSP_MASK 0x80
222 #define CS43130_PDN_ASP_MASK 0x40
224 #define CS43130_PDN_DSPIF_MASK 0x20
226 #define CS43130_PDN_HP_MASK 0x10
228 #define CS43130_PDN_XTAL_MASK 0x08
230 #define CS43130_PDN_PLL_MASK 0x04
232 #define CS43130_PDN_CLKOUT_MASK 0x02
237 #define CS43130_HP_IN_EN_MASK 0x08
240 #define CS43130_ASP_3ST_MASK 0x01
241 #define CS43130_XSP_3ST_MASK 0x02
244 #define CS43130_PLL_DIV_DATA_MASK 0x000000FF
245 #define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT 0
254 #define CS43130_SP_M_LSB_DATA_MASK 0x00FF
255 #define CS43130_SP_M_LSB_DATA_SHIFT 0
258 #define CS43130_SP_M_MSB_DATA_MASK 0xFF00
262 #define CS43130_SP_N_LSB_DATA_MASK 0x00FF
263 #define CS43130_SP_N_LSB_DATA_SHIFT 0
266 #define CS43130_SP_N_MSB_DATA_MASK 0xFF00
270 #define CS43130_SP_LCHI_DATA_MASK 0x00FF
271 #define CS43130_SP_LCHI_LSB_DATA_SHIFT 0
277 #define CS43130_SP_LCPR_DATA_MASK 0x00FF
278 #define CS43130_SP_LCPR_LSB_DATA_SHIFT 0
293 #define CS43130_XTAL_IBIAS_MASK 0x07
296 #define CS43130_MUTE_MASK 0x03
297 #define CS43130_MUTE_EN 0x03
300 #define CS43130_DSD_MASTER 0x04
303 #define CS43130_DSD_SRC_MASK 0x60
306 #define CS43130_DSD_SPEED_MASK 0x04
311 #define CS43130_MIX_PCM_PREP_MASK 0x02
313 #define CS43130_MIX_PCM_DSD_SHIFT 0
314 #define CS43130_MIX_PCM_DSD_MASK 0x01
317 #define CS43130_HP_MEAS_LOAD_MASK 0x000000FF
318 #define CS43130_HP_MEAS_LOAD_1_SHIFT 0
333 CS43130_DSD_SRC_DSD = 0,
339 CS43130_ASP_SPRATE_32K = 0,
351 CS43130_MCLK_SRC_EXT = 0,
357 CS43130_MCLK_24P5 = 0,
369 CS43130_ASP_PCM_DAI = 0,
480 #define HP_LEFT 0