Lines Matching +full:5 +full:b00
34 #define CS42L84_PLL_LOCK_STATUS_ERROR BIT(5)
47 #define CS42L84_CCM_CTL1_MCLK_F_12MHZ 0b00
57 #define CS42L84_CCM_SAMP_RATE_RATE_96KHZ 5
81 #define CS42L84_RING_SENSE_CTL_FALLTIME GENMASK(5, 3)
85 #define CS42L84_TIP_SENSE_CTL_FALLTIME GENMASK(5, 3)
92 #define CS42L84_TIP_SENSE_CTL2_MODE_DISABLED 0b00
95 #define CS42L84_TIP_SENSE_CTL2_INV BIT(5)
103 #define CS42L84_MIC_DET_CTL1_HS_DET_LEVEL GENMASK(5, 0)
113 #define CS42L84_MSM_BLOCK_EN2_BUS_SHIFT 5
121 #define CS42L84_HS_DET_CTL2_SET GENMASK(5, 4)
128 #define CS42L84_HS_SWITCH_CTL_HSB_FILT_HS3 BIT(5)