49 	int bclk;  member
246 	SND_SOC_DAPM_SUPPLY("BCLK", CS42L84_ASP_CTL, CS42L84_ASP_CTL_BCLK_EN_SHIFT, 0, NULL, 0),
270 	{"SDIN1", NULL, "BCLK"},
271 	{"SDIN2", NULL, "BCLK"},
276 	{"SDOUT1", NULL, "BCLK"},
346 	u32 bclk;  member
357  * Common PLL Settings for given BCLK
373 	clk = cs42l84->bclk;  in cs42l84_pll_config()
377 		if (pll_ratio_table[cs42l84->pll_config].bclk == clk)  in cs42l84_pll_config()
384 		if (pll_ratio_table[i].bclk == clk) {  in cs42l84_pll_config()
398 			"Unsupported bclk %d/sample rate %d\n",  in cs42l84_pll_config()
551 		cs42l84->bclk = 0;  in cs42l84_set_sysclk()
556 		if (pll_ratio_table[i].bclk == freq) {  in cs42l84_set_sysclk()
557 			cs42l84->bclk = freq;  in cs42l84_set_sysclk()
562 	dev_err(component->dev, "BCLK %u not supported\n", freq);  in cs42l84_set_sysclk()