Lines Matching +full:1 +full:khz
65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
126 #define HCFG_MONO 0x00000080 /* 1 = I2S Input mono */
127 #define HCFG_I2S_OUTPUT 0x00000010 /* 1 = I2S Output disabled */
128 #define HCFG_AC97 0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */
129 #define HCFG_LOCK_PLAYBACK_CACHE 0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */
131 #define HCFG_LOCK_CAPTURE_CACHE 0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */
134 /* Should be set to 1 when the EMU10K1 is */
137 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
140 * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in.
141 * bit 9 0 = Mute / 1 = Analog out.
142 * bit 10 0 = Line-in / 1 = Mic-in.
143 * bit 11 0 = ? / 1 = ?
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
145 * bit 13 0 = ? / 1 = ?
146 * bit 14 0 = Mute / 1 = Analog out
147 * bit 15 0 = ? / 1 = ?
153 * GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin.
183 /* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
208 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3
209 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground
210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.
211 …* Standard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Shield on all th…
223 #define SPCS1 0x42 /* SPDIF output Channel Status 1 register. For Front */
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
233 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
234 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
248 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
249 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
251 /* When Channel set to 1: */
293 * Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit)
294 * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate)
295 * SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass)
297 /* When Channel = 1:
299 * SPDIF 1 User data [15:8]
307 * When Channel = 1: Bits the same as SPCS channel 1.
316 #define CAPTURE_SOURCE_CHANNEL2 0x00f00000 /* 1 - What you hear or . 2 - ?? */
319 …/* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to…
321 * Record source select for channel 1 [22:20]
325 * 1 - i2s mixer output.
335 #define ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to …
337 …ER_LFE 0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */
342 * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
354 * SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0
414 /* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */
416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
418 * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source.
419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
421 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
422 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
423 * I2S output source select [18] (0=Audio from host, 1=Audio from SRC)
425 * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.)
426 * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.)
427 * I2S input mode [23] (0=Slave, 1=Master)
428 * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
429 * SPDIF output source select [26] (0=host, 1=SRC)
431 * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
432 * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
434 /* Sample rate output control register Channel=1
437 * I2S Input 1 volume Right [23:16]
438 * I2S Input 1 volume Left [31:24]
481 #define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */
506 #define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1
531 #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
533 #define PCM_REAR_CHANNEL 1
538 #define CONTROL_CENTER_LFE_CHANNEL 1
547 #define SPI_RDA1_REG 1
556 #define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */
562 #define SPI_PL_BIT_L_L (1<<5) /* left channel = left */
566 #define SPI_PL_BIT_R_L (1<<7) /* right channel = left */
574 #define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */
578 #define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */
580 #define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */
583 #define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */
588 #define SPI_MS_BIT (1<<5) /* master mode */
591 #define SPI_RATE_BIT_192 (1<<6)
602 #define SPI_DMUTE0_BIT (1<<3)
603 #define SPI_DMUTE1_BIT (1<<4)
604 #define SPI_DMUTE2_BIT (1<<5)
605 #define SPI_DMUTE4_BIT (1<<2)
611 #define SPI_PHASE0_BIT (1<<6)
612 #define SPI_PHASE1_BIT (1<<7)
613 #define SPI_PHASE2_BIT (1<<8)
614 #define SPI_PHASE4_BIT (1<<3)
617 #define SPI_PDWN_BIT (1<<2)
622 #define SPI_DACD0_BIT (1<<1)
623 #define SPI_DACD1_BIT (1<<2)
624 #define SPI_DACD2_BIT (1<<3)
625 #define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */
628 #define SPI_PWRDNALL_BIT (1<<4)
653 ac97 = 1 -> Default to AC97 in. */
654 int gpio_type; /* gpio_type = 1 -> shared mic-in/line-in
656 int i2c_adc; /* with i2c_adc=1, the driver adds some capture volume