Lines Matching +full:gen +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
42 /* 3=Unix Timer */
49 /* 3=AES Out */
56 /* 1=Bresenham Clock Gen 1 */
57 /* 2=Bresenham Clock Gen 2 */
58 /* 3=Bresenham Clock Gen 3 */
120 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
122 #define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
136 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
138 #define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
152 #define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
154 #define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
177 #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
191 u32 _unused1[3];
193 u32 _unused2[3];
195 u32 _unused3[3];
197 u32 _unused4[3];
199 u32 _unused5[3];
201 u32 _unused6[3];
202 u32 idr3; /* 0x70 Indirect Data Register 3 */
212 u32 tx_cr[3]; /* Control registers */