Lines Matching +full:enable +full:- +full:modem +full:- +full:interrupt

1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
11 #define POCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
14 #define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
15 #define PICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
18 #define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
19 #define MCCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
23 #define GCR_CLKBPB	(1 << 31)	/* Internal clock enable */
25 #define GCR_nDMAEN	(1 << 24)	/* non DMA Enable */
26 #define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
27 #define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
28 #define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
29 #define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
30 #define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
31 #define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
32 #define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
35 #define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
43 #define PISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
48 #define MCSR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
58 #define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
59 #define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
62 #define GSR_MCINT	(1 << 7)	/* Mic In Interrupt */
63 #define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
64 #define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
65 #define GSR_ACOFFD	(1 << 3)	/* AC-link Shut Off Done */
66 #define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
67 #define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
68 #define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
74 #define MCDR		(0x0060)  	/* Mic-in FIFO Data Register */
76 #define MOCR		(0x0100)  	/* Modem Out Control Register */
78 #define MOCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
80 #define MICR		(0x0108)  	/* Modem In Control Register */
82 #define MICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
84 #define MOSR		(0x0110)  	/* Modem Out Status Register */
88 #define MISR		(0x0118)  	/* Modem In Status Register */
90 #define MISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
93 #define MODR		(0x0140)  	/* Modem FIFO Data Register */
97 #define PMC_REG_BASE	(0x0400)  	/* Primary Modem Codec */
98 #define SMC_REG_BASE	(0x0500)  	/* Secondary Modem Codec */