Lines Matching full:cpu1

22  * CPU1 after the IPI-induced memory barrier:
24  *         CPU0                              CPU1
38  * The write to y and load from x by CPU1 are unordered by the hardware,
46  * before the IPI-induced memory barrier on CPU1.
56  * order to enforce the guarantee that any writes occurring on CPU1 before
60  *         CPU0                              CPU1
80  * after the IPI-induced memory barrier on CPU1.
84  *           CPU0                            CPU1
102  * and Thread B).  Thread A runs on CPU0, Thread B runs on CPU1.
104  *           CPU0                            CPU1
118  *           CPU0                            CPU1